Cirrus Logic AN368 - Manual (Page 40)

AN368
40 AN368REV2
Step 10) Determine Boost Output Capacitor
The boost stage output capacitor is also the flyback stage input capacitor. Determine the size of the boost
output capacitor using the following points:
• For a 120V line input system, capacitor C6 > 2
F/Watt of input power
• For a 230V line input system, capacitor C6 > 0.5 F/Watt of input power
Proper capacitor size is required to ensure that the following dimmer algorithms execute properly:
• Transition CCM to CRM properly
• No erroneous CCM events
• No CCM operation with trailing-edge dimmers
• No CCM operation in No-dimmer Mode
• Boost and flyback stages loop stability
• Smooth flicker-free behavior during fast conduction-angle transitions
Step 11) Determine Boost Input Capacitor
To be compatible with a wide range of dimmers, the boost input capacitance should be minimized. Large input
capacitance impacts the ability of the controller to properly sustain the current required by the dimmer and may
cause oscillation. Capacitors should not be connected to the AC line side of the bridge rectifier. Added AC line-
side capacitance alters the dimmer behavior in multi-lamp configurations and shifts the dimming curve.
Excessive capacitance on capacitor C1 and after the bridge rectifier generates current spikes that may
introduce ringing. The ringing causes a TRIAC to prematurely open its switches.
3.5 Completing the Design
Step 12) Choose Power Components
The voltage rating of boost FET Q1 and diode D4 can be estimated by adding 20% to the V
BST
. 20% is a
standard margin for safety purposes and prevents damage to the components during abnormal or transient
conditions. Lower voltage ratings can be used, but sufficient testing is necessary to ensure proper operation.
Boost output voltage V
BST
is 405V or 200V for an AC input voltage of 230VAC or 120VAC, respectively. The
breakdown voltage for both the FET and the boost diode ≥ 1.2
·
V
BST
. The boost diode must be ultrafast with
a recovery time of no greater than 50ns and rated for a DC current, as calculated using Equation 64.
Step 13) Bias Circuit
The bias circuit is built using the following components: capacitors C23, C17, and C13, resistor R36, diodes
D1 and D7, and zener diode Z2 (see Figure 1 on page 9). When AC power is first applied, current flows
through capacitor C23 charging capacitor C17, which biases boost transistor Q1 into conduction. Once the
bias circuit turns ‘ON’ boost transistor Q1, a current is applied to pin VDD through diode D2.
The initial supply current I
DD
flows through transistor Q1 onto capacitors C12 and C11. Zener diode Z2 limits
the charge on capacitor C17. The initial supply voltage V
DD
applied to pin VDD is defined by Equation 65.
Resistor R36 limits the current in capacitor C23. Once the voltage applied to pin VDD has exceeded the UVLO
voltage, the CS1630 starts to operate, and voltage appears at the boost inductor L3 auxiliary winding. When
transistor Q1 is ‘ON’, capacitor C5 charges from diode D3 to pin GND. When transistor Q1 is ‘OFF’, capacitor
C5 reroutes the charge into capacitor C11 from diode D3. As the voltage develops across capacitor C11 and
exceeds V
DD
, transistor Q4 turns ‘ON,’ and diode D2 reverse biases. After startup, transistor Q4 supplies V
DD
to the device with the larger current required during normal operation. See Equation 66.
The inequality in Equation 66 indicates that diode D2 is back biased after start up.
V
DD
V
Z2
V
Q2 th  
V
D6
– – =
[Eq. 65]
V
DD
V
Z2
V
Q1 th  
–   V
Z2
V
Q2 th  
V
D6
– –    = [Eq. 66]