Cirrus Logic AN368 - Manual (Page 44)

AN368
44 AN368REV2
e. Short Circuit Protection
Short circuit protection (SCP) is designed to detect when either of the channels is short circuited and prevents
the second stage from operating in continuous current mode (CCM). The charge regulation loop is monitored
using a digital algorithm that detects SCP events and is enabled when bit SCP is set to ‘0’. Bit SCP is bit 1 in
register Config16 at Address 48.
f. Voltage Difference Protection
Voltage difference protection (VDIFF) is designed to detect when the channel with the lower voltage is open
circuited. For example, when the second channel is disconnected or open circuited, the voltage on channel 2
slightly exceeds the voltage on channel 1, and the internal charge regulation loop in the CS1630 detects the
difference and creates a VDIFF event in the IC. VDIFF protection is different from overvoltage protection (OVP)
and requires an independent process. In the OVP case, a fault is not generated if the lower voltage channel is
open circuited. The charge regulation loop is monitored using a digital algorithm that detects VDIFF events
using the OTP settings configured in the following steps:
1. The voltage difference protection feature is enabled when bit VDIFF is set to ‘0’. Bit VDIFF is bit 0 in
register Config16 at Address 48.
2. Configure VDIFF faults to be of type unlatched or latched. Set bit VDIFF_LAT to ‘1’ for latched faults. Bit
VDIFF_LAT is bit 1 in register Config45 at Address 77. Unlatched VDIFF faults are cleared and restarted
using the configuration in Step 15a Protection Restart on page 41. Latched VDIFF faults are not cleared
until the power to the IC is recycled.
g. Boost Overvoltage Protection
Boost overvoltage protection (BOP) is designed to detect when the boost voltage exceeds a specified
threshold. Boost overvoltage protection is implemented by monitoring the boost output voltage applied to the
bulk capacitor at the boost output. The voltage applied to pin BSTOUT is measured against a programmable
threshold voltage V
BOP(th)
. The measured output is monitored using a digital algorithm that detects BOP
events using the OTP settings configured in the steps below:
1. The boost overvoltage protection feature is enabled when bit BOP is set to ‘0’. Bit BOP is bit 4 in register
Config47 at Address 79.
2. Configure BOP threshold voltage V
BOP(th)
to be 0V to 30V above the clamp turn-on voltage setting,
which is 227V for a 120V IC. The threshold value can be configured using bits BOP_THRES[3:0] in
register Config53 at Address 85. BOP threshold voltage V
BOP(th)
is calculated using Equation 71:
This value is limited internally to 254V for a 120V IC. The BOP does not trip immediately when the boost
output voltage crosses this threshold, unless BOP_INTEG[2:0] equals 0 (no filter).
3. Configure the leaky integrator output threshold for declaring a BOP fault. The BOP event signal is
averaged continuously using a leaky integrator, and a BOP fault is declared if the averaged value
exceeds the output threshold set by bits BOP_INTEG in register Config53 at Address 85. When V
BST
exceeds the set threshold BOP_THRES[3:0], the leaky integrator uses these parameters: feedback
coefficient = 63/64; sample rate = 12.5kHz; input = 8. If bits BOP_INTEG[2:0] = ‘000’ a BOP fault trips
immediately when V
BST
crosses the threshold (no filter). Otherwise the integrator output threshold is an
integer from 1 to 7.
4. Configure boost BOP fault behavior. When bit BOP_RSTART in register Config54 at Address 86 is set
to ‘1’ the IC attempts to restart after the boost output voltage V
BST
drops down to a nominal voltage level.
It is recommended to enable bit MAX_CUR in register Config45 at Address 77 when BOP_RSTART
equals 1 so the second stage can deliver full output power when a boost BOP fault is detected. This
helps quickly dissipate the energy stored in the boost output capacitor, bringing down the voltage on the
capacitor. When bit BOP_RESTART is set to ‘0’, the BOP fault is latched and cleared when power to
the IC is recycled.
V
BOP th  
BOP_THRES  [3:0] 2  227V +  = [Eq. 71]