Cirrus Logic AN368 - Manual (Page 28)

AN368
28 AN368REV2
Time T2
CHx
offset delays cause errors when calculating average current regulation using Equations 27 and
28. Averaged output current I
MODEx
of a flyback converter is illustrated in Figure 10.
V
A UX
Zero-cross
Detection
D15
D2
R22
Z3
R
S ense
R23
Q5
CS1630 /31
FBAUX
GND
13
GD
FBSENSE
15
12
11
TX1
V
B S T
Snubber
I
MODE x
Synchronizer
Circuit
I
S ense
C8
C15
D5
Channel 1 LED
(White)
Channel 2 LED
(Red)
Q3
V
MODE x
I
P RI
GND
IGND
V
Drain
C
P
Figure 10. Flyback Configuration