Cirrus Logic AN368 - Manual (Page 42)

AN368
42 AN368REV2
b. Overcurrent Protection
Overcurrent protection (OCP) is designed to detect when the current-sensing resistor R
Sense
is open circuited
or unusually large. Overcurrent protection is implemented by monitoring the voltage across the sense resistor
R
Sense
. The voltage applied to pin FBSENSE is fed to a comparator and measured against a threshold voltage
V
OCP(th)
of 1.69V. The comparator output is monitored using a digital algorithm that detects OCP events using
the OTP settings configured in the following steps:
1. The overcurrent protection feature is enabled when bit OCP is set to ‘0’. Bit OCP is bit 7 in register
Config47 at Address 79.
2. Configure OCP faults to be of type unlatched or latched. Set bit OCP_LAT to ‘1’ for latched faults. Bit
OCP_LAT is bit 4 in register Config49 at Address 81. Unlatched OCP faults are cleared and restarted
using the configuration in Step 15a Protection Restart on page 41. Latched OCP faults are not cleared
until the power to the IC is recycled.
3. Configure the OCP blanking time using bits OCP_BLANK[3:0] in register Config48 at Address 80. The
OCP blanking time starts at the rising edge of the gate drive and should be configured to blank out
switching noise on pin FBSENSE, which can trigger an OCP event. It is recommended to set the OCP
blanking time to less than the leading-edge blanking time for the second-stage peak current
measurement by at least one clock cycle. For proper operation, an OCP event must be recorded prior
to starting a nominal measurement of the second-stage peak current regulated by the feedback control
loop. When the peak current reaches the regulated threshold, the gate drive turns ‘OFF’, and if the OCP
blanking time is programmed to overlap this process, a missed OCP event is possible.
4. Configure the threshold for the OCP event accumulator used to declare an OCP fault. Bits
OCP_CNT[2:0] in register Config49 at Address 81 are used to configure the threshold. If the voltage on
pin FBSENSE exceeds 1.69V after the time the second-stage gate drive is turned ‘ON’ and outside of
the OCP blanking window, then the OCP event accumulator is incremented by 1 after the gate drive
turns ‘OFF’. If an OCP event does not occur during this time, the event accumulator is decremented by
1. Once the accumulator count exceeds or equals the threshold set by bits OCP_CNT[2:0], an OCP fault
is declared, and the system enters a fault state. Hence, the value defined by bits OCP_CNT[2:0] sets
the minimum number of consecutive second-stage gate drive switching cycles that encountered an
OCP event declaring a system OCP fault. The OCP event accumulator is required to assist in preventing
the system from declaring a fault due to glitches and random noise. When an OCP fault is declared, the
fault behavior during the fault state is determined by bit FAULT_SHDN (see Step 15a Protection Restart
on page 41).
c. Open Loop Protection
Open loop protection (OLP) is designed to detect when the current-sensing resistor R
Sense
is shorted and
when the output is an open circuit. The voltage applied to pin FBSENSE is fed to a comparator and measured
against a threshold voltage V
OLP(th)
of 200mV. The comparator output is monitored using a digital algorithm
that detects OLP events using the OTP settings configured in the following steps:
1. The OLP feature is enabled when bit OLP is set to ‘0’. Bit OLP is bit 6 in register Config47 at Address 79.
2. Configure OLP faults to be of type unlatched or latched. Set bit OLP_LAT to ‘1’ for latched faults. Bit
OLP_LAT is bit 0 in register Config49 at Address 81. Unlatched OLP faults are cleared and restarted
using the configuration in Step 15a Protection Restart. Latched OLP faults are not cleared until the
power to the IC is recycled.
3. Configure the OLP blanking time using bits OLP_BLANK[2:0] in register Config48 at Address 80. The
OLP blanking time starts at the rising edge of the gate drive and should be configured such that the
blanking window is slightly greater than the minimum time required for a voltage applied to pin
FBSENSE to exceed 200mV. After the gate drive turns ‘ON’ and the blanking window elapses, the digital
process waits 250ns to allow the digital algorithm to scan for an OLP event. If the comparator circuit
does not trip, the gate drive is disabled, and an OLP fault is logged. If the blanking window is too long
the power converter may not be properly protected, and if the window is too short, a false OLP fault may
be logged.