Cirrus Logic AN368 - Manual (Page 61)

AN368
AN368REV2 61
f. Procedure for Measuring the Second-stage Output Current Regulation
Measurement of second-stage output current regulation is required even though T2 commutation time delay
compensation is disabled. The tuning process has accounted for all the circuit parasitics that cause errors in
the output current regulation. The final step is to measure the output current regulation as described in
Step 4f Procedure for Measuring the Second-stage Output Current Regulation on page 31. The tuning process
may require a couple of iterations before obtaining the correct combination of register values that result in the
optimum target output current regulation.
Step 6) Synchronizer Circuit Design
a. Phase Synchronization
The programmable threshold for the synchronization is programmed through the EXIT_PH[3:0] and
DECL_PH[3:0] bits in register Config15 at Address 47. Bits EXIT_PH[3:0] configure the minimum number of
switching cycles between synchronization events, and bits DECL_PH[3:0] configure the number of exceptions
before declaring a synchronization. Phase synchronization is enabled by asserting the RESYNC bit in register
Config17 at Address 49.
Design Tip - Red channel current oscillates between two target current levels upon power-up
Symptoms:
The output current on the red channel varies by a large amount between two
distinct target current levels between system power-ups.
Cause: The most likely cause for this is that the logic inside the controller that detects that
the sync signal is out of phase and performs a re-sync is not enabled. Depending
on how the external Synchronizer Circuit aligns its phase when the system is first
powered up, the target current settling level may be different.
Solution: Enable the re-syncing feature by asserting the RESYNC bit in the Config17 register
at Address 49.
b. Flyback Mode Operation Using a Dual LED String Synchronizer Circuit
Figure 14 on page 33 is a design example of the Synchronizer Circuit in a 120VAC, 9W flyback converter
application circuit with series load configuration. Nominal boost output voltage V
BST
is 200V, and the output
voltage when both LED strings are conducting is approximately 38V at the highest light output. The flyback
inductance is 3.65mH, and the turns ratio of the transformer winding is 5.57:1. Resistor R3 is set to 5.6k
 to
prevent the CLK node from rising too high. Voltage regulator diode D9 is 5.1V, 500mW with a current of 5mA.
Resistor R12 is selected to be 10k
 and in conjunction with diode D10 is the dominant path from the output
voltage to supply power to the flip-flop.
The turns ratio can be increased or a regulator diode with lower reverse current can be used to decrease the
power loss on resistor R10. Depending on the turns ratio of the secondary winding and the main duty cycle of
the converter, the first path may not provide enough current. In that case, resistor R3 should be selected so
that Equation 58 is satisfied:
c. Synchronizer Circuit RC Filter Design
The U2 flip-flop, SN74LVC1G80, is a single positive-edge triggered D-type flip-flop. In this design example, a
noise glitch was observed on the clock input, D of the D flip-flop, approximately 400ns to 500ns after the falling
edge of gate drive. Resistor R2 and capacitor C16 form an RC filter used to suppress noise on flip-flop U2
clock pin. Lab results show that resistor R2 = 10k
 and capacitor C16 = 47pF with time constant = 470ns
filters any noise on the U2 clock pin and the resulting Q signal is stable. The noise events are design
dependent and should be reviewed when major changes occur to the secondary power train, for example the
inductor or transistor.
I
D9
I
sync rms  
V
MODEx
R 3
-------------------- + = [Eq. 130]
