Cirrus Logic AN368 - Manual (Page 68)

AN368
68 AN368REV2
j. External Overtemperature Protection
The external negative temperature coefficient (NTC) thermistor reference is a Murata NCP18WF104J03RB.
This NTC is 100k
 with a Beta of 4275. If the temperature exceeds 95°C, R
NTC
is approximately 6.3k  and
resistor R29 is 14k , so the eOTP pin has a total resistance of 20.3k. Solving Equation 75 for
CODE
TEMPeOTP
:
The eOTP circuit initiates a protective dimming action at 125°C. A temperature of 125°C corresponds to a
thermistor resistance equal to 2.5k
 plus resistor R18 equal to 14k which presents a resistance of 16.5k
at pin eOTP, reaching the point at which a thermal shutdown fault intervenes. Solving Equation 75 for
CODE
TEMPShutdown
:
The OTP settings are configured using the following:
1. Set bit EEOTP in register Config47 at Address 79 to ‘0’ to enable external overtemperature protection
2. Set bit BOOST_ON in register Config53 at Address 85 to ‘0’, which enables boost after a eOTP
measurement check for Temp
NTC
> Temp
Wakeup
3. Set bits eOTP[4:0] in register Config59 at Address 91 to ‘11110’, which configures the 8-bit code value
CODE
TEMPeOTP
to 200
4. Set bits WAKEUP[3:0] in register Config46 at Address 78 to ‘0101’, which configures the 8-bit code
value CODE
TEMPWakeup
to 220
5. Set bits SHUTDWN[3:0] in register Config58 at Address 90 to ‘0101’, which configures the 8-bit code
value CODE
TEMPShutdown
to 240
6. Set bits EOTP_FLP[2:0] in register Config55 at Address 87 to ‘100’ to set the time constant of the first
(faster) low-pass filter used for filtering the coarse 8-bit ADCR temperature to 1.866s
7. Set bits EOTP_SLP[2:0] in register Config55 at Address 87 to ‘110’ to set the time constant of the
second (slower) low-pass filter used for filtering the coarse 8-bit ADCR temperature to 1min
8. Set bits RATE[1:0] in register Config44 at Address 76 to ‘11’ to set the dimming rate for the external
overtemperature protection feature to 32 dims per temperature code above CODE
TEMPeOTP
9. Enable the second-stage dim level adjustment process by setting bit DIM_TEMP in register Config58 at
Address 90 to ‘1’
10. Set bits LOW_SAT[2:0] in register Config58 at Address 90 to ‘001’ to configure the lower saturation limit
CODE
LOWSAT
to 10
11. Set bits HI_SAT[2:0] in register Config59 at Address 91 to ‘100’ to configure the higher saturation limit
CODE
HISAT
to 160
k. Internal Overtemperature Protection
The OTP settings are configured using the following:
1. Set bit IOTP in register Config47 at Address 79 to ‘0’ to enable the internal overtemperature protection
2. Set bit IOTP_SAMP in register Config48 at Address 80 to ‘1’ to sample the internal temperature sensor
at a slow rate when not in a iOTP fault
Step 16) Clamp Circuit
Clamp load resistors R9 and R11 must each be 2k
2W resistors for 120V systems. This value has been
validated for optimal dimming performance.
CODE
TEMPeOTP
4M 
R
NTC
R
S
+  
--------------------------------
4M 
6.3k  14k +  
------------------------------------------ 197 = = = [Eq. 142]
CODE
Shutdown
4M 
R
NTC
R
S
+  
--------------------------------
4M 
2.5k  14k +  
------------------------------------------ 242 = = =
[Eq. 143]