Cirrus Logic AN368 - Manual (Page 60)

AN368
60 AN368REV2
2. Disabling automatic T
RES
probing and fixing the T
RES
probe count will resolve the
problem. This has the disadvantage that if the resonant frequency differs by a lot due
to board-to-board or component-to-component variations, then the fixed value will not
be accurate.
Step 5) Optimize Output Current Regulation
a. Definition and Scope of Second-stage Output Current Regulation
Calculate channel 1 LED string current I
CH1
and channel 2 LED string current I
CH2
using Equations 48 and 49:
where,
dim = The 12-bit dim level provided by the boost stage
I
CH1(fb)
= Current at full brightness, when the dim is 4095 (full scale) provided that the color system is disabled
Measure I
PK(FB)
and calculate the percentage error, I
error
, at any specified dim using Equation 50:
where,
I
calculate
= Current calculated in Equations 125 and 126
b. Tune Flyback ZCD Fixed Delays for Optimum Valley-switching Performance
To minimize switching losses, the valley-switching performance was optimized using the steps detailed in Step
5b Tune Flyback ZCD Fixed Delays for Optimum Valley-switching Performance on page 25. Channel 1 ZCD
time delay T
CH1ZCD(Delay)
was fixed to 300ns by setting bits CH1_ZCD[2:0] in register Config8 at Address 40
to ‘110’. Channel 2 ZCD time delay T
CH2ZCD(Delay)
was fixed to 50ns by setting bits CH2_ZCD[2:0] in register
Config16 at Address 48 to ‘001’. Disabling bit T2COMP signifies to the algorithm that bits RE1_ZCD[2:0] and
RE2_ZCD[2:0] are not used.
c. Tune I
PK(FB)
Compensations for Optimum Linear Performance
The peak current versus the gate drive ‘ON’ time was measured and T1
comp
was determined to be
approximately 350ns. The actual peak current was adjusted by setting bits CS_DELAY[2:0] in register
Config60 at Address 92 to ‘111’. The optimized peak current I
PK(FB)
was derived using Equation 51.
d. Set T2 Offset Delays to Get Optimum Linear Performance
Times T2
CH1OFF
and T2
CH2OFF
are offset delays that assist in achieving the desired linear performance on the
output currents across dim on the second stage. Configure offset bits CH1_OFF[2:0] in register Config62 at
Address 94 to ‘101’ and use Equation 53 to calculate the time T2
CH1OFF
:
Configure offset bits CH2_OFF[2:0] in register Config62 at Address 94 to ‘111’ and use Equation 53 to
calculate the time T2
CH2OFF
:
e. T2 Commutation Time Delay Compensation
The T2 commutation time delay does not have a significant effect on regulation and is disabled by setting bit
T2COMP to ‘0’ in register Config2 at Address 34. Disabling bit T2COMP signifies to the algorithm that bits
T2CH1GAIN[5:0], T2CH2GAIN[5:0], RE1_ZCD[2:0], and RE2_ZCD[2:0] are not used.
I
CH1
I
CH1 fb  
dim 
4095
---------------------------------
488mA 1024 
4095
------------------------------------- 122mA = = = [Eq. 125]
I
CH2
I
CH2 fb  
dim 
4095
---------------------------------
213mA 1024 
4095
------------------------------------- 53.3mA = = = [Eq. 126]
I
error
I
calculate
I
measure
–
I
calculate
---------------------------------------------- 100  = [Eq. 127]
T2
CH1OFF
CH1_OFF[2:0] 50ns  5 50ns  250ns = = = [Eq. 128]
T2
CH2OFF
CH2_OFF[2:0] 50ns  7 50ns  350ns = = = [Eq. 129]