Cirrus Logic AN368 - Manual (Page 67)

AN368
AN368REV2 67
Design Tip - Prevent output current from exceeding V
OVP(th)
if one channel is open circuited
Check: Determine if the power supply is operating in either auto-restart or latch mode when
load is open and output voltage reaches the threshold. The comparator threshold
is set to 1.25V, which should translate to a particular voltage level on the primary
side.
Test Stimulus: Unplug one or both of the loads.
Performance:
Once the output voltage reaches the threshold, the power supply is protected in
either auto-restart or latch mode, depending on the OTP setting.
Note that if only one of the load channels is opened, depending on if the output load
configuration is parallel or series, OVP may or may not be actuated depending on
which channel was opened. This type of a fault may show up as a VDIFF event.
e. Short Circuit Protection
The OTP settings are configured by setting bit SCP in register Config16 at Address 48 to ‘0’ to enable short
circuit protection.
f. Voltage Difference Protection
The OTP settings are configured using the following:
1. Set bit VDIFF in register Config16 at Address 48 to ‘1’ to disable V
Diff
fault
2. Set bit VDIFF_LAT in register Config45 at Address 77 set to ‘0’ to configure the VDIFF fault type as
unlatched
g. Boost Overvoltage Protection
The OTP settings are configured using the following:
1. Set bit BOP in register Config47 at Address 79 to ‘0’ to enable boost overvoltage protection
2. Set bits BOP_THRES[3:0] in register Config53 at Address 85 to ‘1011’ for a threshold voltage V
BOP(th)
of 249V
3. Set bits BOP_INTEG[2:0] in register Config53 at Address 85 to ‘111’ for an integrator output threshold
of 7
4. Set bit MAX_CUR in register Config45 at Address 77 to ‘1’ to allow the second stage to draw maximum
power when V
BST
> V
BOP(th)
Set bit BOP_RSTART in register Config54 at address 86 to ‘1’ to attempt a restart if V
BST
equals 392V
h. Clamp Overpower Protection
The OTP settings are configured using the following:
1. Set bit COP in register Config47 at Address 79 to ‘0’ to enable clamp overvoltage protection
2. Set bit COP_INT in register Config52 at Address 84 to ‘0’ for a 1-second interval to check for a boost
stage COP fault
3. Set bits COP_THRES[6:0] in register Config52 at Address 84 to ‘0010000’ to set the time-on threshold
T
ON(th)
for a 1-second interval to 84.5ms
i. Link Line Protection
The OTP settings are configured using the following:
1. Set bit LLP in register Config47 at Address 79 to ‘0’ to enable link line protection
2. Set bits LLP_TIME[2:0] in register Config54 at Address 86 to ‘010’ to set a time window of 2ms that the
condition V
BST
<(V
Line
-V
LLPMin(th)
) is true before asserting a boost LLP fault
Set bits BST_LLP[1:0] in register Config62 at Address 94 to ‘01’ for a minimum threshold voltage V
LLP-
Min(th)
that is 80V; when the condition V
BST
<(V
Line
-80V) occurs, an LLP fault is triggered