Artesyn PrAMC-7311 Installation and Use (June 2014) - Manual (Page 55)

Address Mapping
PrAMC-7311 Installation and Use (6806800P34D) 55
5.5 GPIO Mapping
The following table shows the relation between the GPIO signals and pins.
00 1D 0 USB 1.1 OHCI Controller 1 2688 Intel 3100 A1
00 1D 1 USB 1.1 OHCI Controller 2 (Not used) 2689 Intel 3100 A1
00 1D 7 USB 2.0 EHCI Host Controller 268C Intel 3100 A1
00 1E 0 PCI-to-PCI Bridge 244E Intel 3100 A1
00 1F 0 ISA Bridge (LPC Interface) 2670 Intel 3100 A1
00 1F 2 SATA Host Controller 2680 Intel 3100 A1
00 1F 3 SMBus Controller 269B Intel 3100 A1
20 00 0 Gigabit Ethernet Controller (Port 0) 1060 Intel 82571EB D0
20 00 1 Gigabit Ethernet Controller (Port 1) 1060 Intel 82571EB D0
21 00 0 10/100Mbit Ethernet Controller 1229 Intel 82551QM A1
Table 5-4 PCI Device Mapping (continued)
Bus Dev Fun Device DID Vendor Part
Table 5-5 GPIO Mapping
Signal GPIO Pin# Power Rail Description
DRAMRST_CNT
RL_PCH GPIO60 A12 VCC3V3_A Controls DDR3 RESET signal from CPU
PCH_HOTN GPIO74 C13 VCC3V3_A PCH's Thermal status report signal to MMC
NMI GPIO8 C10 VCC3V3_A NMI from MMC to PCH
PCH_GPIO27 GPIO27 E16 VCC3V3_A General Purpose IO pin to MMC from PCH
PCH_GPIO49_T
RALERT GPIO49 V3 VCC3V3_S General Purpose IO pin to MMC from PCH
SATA2GP GPIO36 V8 VCC3V3_S Optional GPI from Device Present pin of SATA slim
line Power connector