BECKHOFF ET1200 - Manual (Page 21)

Pin Description
Slave Controller – ET1200 Hardware Description III-11
3.1.2 Signal Overview
Table 9: Signal Overview
Signal Type Dir. Description
C25_ENA Configuration I CLK25OUT Enable: Enable CLK25OUT
C25_SHI[1:0] Configuration I TX Shift: Shifting/phase compensation of MII TX signals
CLK_MODE[1:0] Configuration I CPU_CLK configuration
CLK25OUT MII O 25 MHz clock source for Ethernet PHY
CPU_CLK PDI O Clock signal for µController
EBUS{1:0}-RX- EBUS LI- EBUS LVDS receive signal -
EBUS{1:0}-RX+ EBUS LI+ EBUS LVDS receive signal +
EBUS{1:0}-TX- EBUS LO- EBUS LVDS transmit signal -
EBUS{1:0}-TX+ EBUS LO+ EBUS LVDS transmit signal +
EEPROM_CLK EEPROM BD EEPROM I 2 C Clock
EEPROM_DATA EEPROM BD EEPROM I 2 C Data
EEPROM_SIZE Configuration I EEPROM size configuration
PERR(1:0) LED O Port receive error LED output (for testing)
GND Power Ground
GND
Core
Power Core logic ground
GND
I/O
Power I/O ground
GND
PLL
Power PLL ground
LINK_MII(1:0) MII I PHY signal indicating a link
LINKACT(1:0) LED O Link/Activity LED output
MI_CLK MII O PHY Management Interface clock
MI_DATA MII BD PHY Management Interface data
MODE[1:0] Configuration I Chip Mode, port configuration
OSC_IN Clock I Clock source (crystal/oscillator)
OSC_OUT Clock O Clock source (crystal)
PDI[17:0] PDI BD PDI signal, depending on EEPROM content
PHYAD_OFF Configuration I Ethernet PHY Address Offset
RBIAS EBUS BIAS resistor for LVDS TX current adjustment
RESET General BD Open collector Reset output/Reset input
RUN LED O Run LED controlled by AL Status register
RX_CLK MII I MII receive clock
RX_D[3:0] MII I MII receive data
RX_DV MII I MII receive data valid
RX_ERR MII I MII receive error
SYNC/LATCH[1:0] DC I/O Distributed Clocks SyncSignal output or LatchSignal input
TESTMODE General I Reserved for testing, connect to GND
TX_D[3:0] MII O MII transmit data
TX_ENA MII O MII transmit enable
V
CC
Power Device power (LDO input)
V
CC Core
Power Core logic power
V
CC I/O
Power I/O power
V
CC PLL
Power PLL power