BECKHOFF ET1200 - Manual (Page 9)

FIGURES
Slave Controller – ET1200 Hardware Description III-IX
FIGURES
Figure 1: ET1200 Block Diagram ............................................................................................................ 1
Figure 2: Frame Processing .................................................................................................................... 2
Figure 3: MII Interface signals ............................................................................................................... 24
Figure 4: TX Shift Timing Diagram ........................................................................................................ 26
Figure 5: MII timing RX signals.............................................................................................................. 27
Figure 6: EBUS Interface Signals .......................................................................................................... 28
Figure 7: ET1200 Digital I/O Signals ..................................................................................................... 30
Figure 8: Digital Output Principle Schematic ......................................................................................... 31
Figure 9: Bidirectional mode: Input/Output connection (R=4.7 k Ω recommended) .............................. 32
Figure 10: Digital Input: Input data sampled at SOF, I/O can be read in the same frame .................... 34
Figure 11: Digital Input: Input data sampled with LATCH_IN ................................................................ 34
Figure 12: Digital Output timing ............................................................................................................. 34
Figure 13: Bidirectional Mode timing ..................................................................................................... 34
Figure 14: SPI master and slave interconnection.................................................................................. 35
Figure 15: Basic SPI_DI/SPI_DO timing (*refer to timing diagram for relevant edges of SPI_CLK) .... 39
Figure 16: SPI read access (2 byte addressing, 2 byte read data) with BUSY and separate status
reading ................................................................................................................................................... 40
Figure 17: SPI write access (2 byte addressing, 1 byte write data) ...................................................... 41
Figure 18: SPI write access (3 byte addressing, 1 byte write data) ...................................................... 42
Figure 19: Distributed Clocks signals .................................................................................................... 43
Figure 20: LatchSignal timing ................................................................................................................ 43
Figure 21: SyncSignal timing ................................................................................................................. 43
Figure 22: I²C EEPROM signals ............................................................................................................ 44
Figure 23: Quartz crystal connection ..................................................................................................... 45
Figure 24: Quartz crystal Clock source for ET1200 and Ethernet PHYs .............................................. 45
Figure 25: Oscillator clock source for ET1200 and Ethernet PHYs ...................................................... 46
Figure 26: ET1200 power supply........................................................................................................... 46
Figure 27: Dual purpose configuration input/LED output pins ............................................................... 47
Figure 28: PHY Connection ................................................................................................................... 47
Figure 29: LVDS termination ................................................................................................................. 48
Figure 30: RBIAS resistor ...................................................................................................................... 48
Figure 31: Reset Logic .......................................................................................................................... 48
Figure 32: Reset Timing ........................................................................................................................ 53
Figure 33: Package Outline ................................................................................................................... 55
Figure 34: Dimensions ........................................................................................................................... 56
Figure 35: Notes .................................................................................................................................... 56
Figure 36: Chip Label ............................................................................................................................ 56
Figure 37: Maximum Soldering Profile .................................................................................................. 58
Figure 38: Example Soldering Profiles .................................................................................................. 58