TABLES
III-VIII
Slave Controller
– ET1200 Hardware Description
Table 1: ET1200 Main Features .............................................................................................................. 1
Table 2: Frame Processing Order ........................................................................................................... 2
Table 3: Revision/Build History................................................................................................................ 3
Table 4: ET1200 Feature Details ............................................................................................................ 4
Table 5: Legend ....................................................................................................................................... 6
Table 6: Legend ....................................................................................................................................... 7
Table 7: Register Overview ..................................................................................................................... 7
Table 8: Pin Overview ........................................................................................................................... 10
Table 9: Signal Overview ....................................................................................................................... 11
Table 10: PDI signal overview ............................................................................................................... 12
Table 11: Chip Mode ............................................................................................................................. 13
Table 12: CPU_CLK Mode .................................................................................................................... 13
Table 13: TX Shift .................................................................................................................................. 13
Table 14: CLK_25OUT Enable .............................................................................................................. 14
Table 15: PHY Address Offset .............................................................................................................. 14
Table 16: SII EEPROM Size .................................................................................................................. 14
Table 17: General pins .......................................................................................................................... 15
Table 18: SII EEPROM pins .................................................................................................................. 15
Table 19: DC SYNC/LATCH and MII Management pins ....................................................................... 16
Table 20: LED pins ................................................................................................................................ 16
Table 21: Combinations of Chip modes and PDIs ................................................................................ 17
Table 22: Port 0/1 and PDI signals (Configuration and chip mode 00) ................................................. 19
Table 23: Port 0/1 and PDI signals (chip modes 10/11) ........................................................................ 19
Table 24: PDI pins ................................................................................................................................. 20
Table 25: Mapping of Digital I/O Interface ............................................................................................. 21
Table 26: Mapping of SPI Interface ....................................................................................................... 21
Table 27: Mapping of EBUS Bridge signals .......................................................................................... 22
Table 28: Mapping of MII Bridge signals ............................................................................................... 22
Table 29: Power supply options (all voltages nomal) ............................................................................ 23
Table 30: Power supply ......................................................................................................................... 23
Table 31: MII Interface signals .............................................................................................................. 25
Table 32: TX Shift Timing characteristics .............................................................................................. 26
Table 33: MII timing characteristics ....................................................................................................... 27
Table 34: EBUS Interface signals ......................................................................................................... 28
Table 35: Available PDIs for ET1200 .................................................................................................... 29
Table 36: ET1200 Digital I/O signals ..................................................................................................... 30
Table 37: Digital I/O timing characteristics ET1200 .............................................................................. 33
Table 38: SPI signals ............................................................................................................................. 35
Table 39: SPI commands CMD0 and CMD1 ......................................................................................... 36
Table 40: Address modes ...................................................................................................................... 36
Table 41: Interrupt request register transmission .................................................................................. 36
Table 42: SPI timing characteristics ET1200 ........................................................................................ 38
Table 43: Read/Write timing diagram symbols ...................................................................................... 39
Table 44: Distributed Clocks signals ..................................................................................................... 43
Table 45: DC SYNC/LATCH timing characteristics ET1200 ................................................................. 43
Table 46: I²C EEPROM signals ............................................................................................................. 44
Table 47: EEPROM timing characteristics ............................................................................................ 44
Table 48: Absolute Maximum Ratings ................................................................................................... 49
Table 49: Operating Conditions ............................................................................................................. 49
Table 50: DC Characteristics ................................................................................................................. 50
Table 51: DC Characteristics (Supply current) ...................................................................................... 51
Table 52: AC Characteristics ................................................................................................................. 52
Table 53: Forwarding Delays ................................................................................................................. 54
Table 54: Absolute Maximum Storage Conditions ................................................................................ 57
Table 55: Example Soldering Profile ..................................................................................................... 59
