BECKHOFF ET1200 - Manual (Page 47)

PDI Description
Slave Controller – ET1200 Hardware Description III-37
6.3.7 Write access
In the data phase of a write access, the SPI master sends the write data bytes to the SPI slave
(SPI_DI/MOSI). The write access is terminated by taking back SPI_SEL after the last byte. The
SPI_DO signal (MISO) is undetermined during the data phase of write accesses.
6.3.8 Read access
In the data phase of a read access, the SPI slave sends the read data bytes to the SPI master
(SPI_DO/MISO).
6.3.8.1 Read Wait State
Between the last address phase byte and the first data byte of a read access, the SPI master has to
wait for the SPI slave to fetch the read data internally. Subsequent read data bytes are prefetched
automatically, so no further wait states are necessary.
The SPI master can choose between these possibilities:

The SPI master may either wait for the specified worst case internal read time t
read
after the last
address/command byte and before the first clock cycle of the data phase.

The SPI master may use the BUSY signaling of the SPI slave to achieve faster read times. The
SPI slave presents its state on SPI_DO (MISO) after SPI_DI (MOSI) is set high between address
and data phase (Busy Out enable) until SPI_DI is set to low (Busy Out enable is edge sensitive) .
While the SPI slave is busy, it will drive SPI_DO high. Once it has finished, SPI_DO is set to low
and the master may start with the next clock cycle for the first read data byte.
BUSY signaling is not available in SPI mode 0/2 with normal data out sample.
6.3.8.2 Read Termination
The SPI_DI signal (MOSI) is used for termination of the read access by the SPI master. For the last
data byte, the SPI master has to set SPI_DI to high (Read Termination byte = 0xFF), so the slave will
not prefetch the next read data internally. If SPI_DI is low during a data byte transfer, at least one
more byte will be read by the master afterwards.
6.3.9 SPI access errors and SPI status flag
The following reasons for SPI access errors are detected by the SPI slave:

The number of clock cycles recognized while SPI_SEL is asserted is not a multiple of 8
(incomplete bytes were transferred).

For a read access, the data phase was not terminated by setting SPI_DI to high for the last byte.

For a read access, additional bytes were read after termination of the access.
A wrong SPI access will have these consequences:

Registers will not accept write data (nevertheless, RAM will be written).

Special functions are not executed (e.g., SyncManager buffer switching).

A status flag will indicate the error until the next access (not for SPI mode 0/2 with normal data out
sample)
A status flag, which indicates if the last access had an error, is available in any mode except for SPI
mode 0/2. The status flag is presented on SPI_DO (MISO) after the slave is selected (SPI_SEL) and
until the first clock cycle occurs. So the status can be read either between two accesses by assertion
of SPI_SEL without clocking, or at the beginning of an access just before the first clock cycle. The
status flag will be high for a good access, and low for a wrong access.
6.3.10 EEPROM_LOADED
The EEPROM_LOADED signal indicates that the SPI Interface is operational. Attach a pull-down
resistor for proper function, since the PDI pin will not be driven until the EEPROM is loaded.