BECKHOFF ET1200 - Manual (Page 24)

Pin Description
III-14 Slave Controller – ET1200 Hardware Description
3.2.4 CLK25OUT Enable
A 25MHz clock for the Ethernet PHY can be made available by the ET1200 on pin PDI[6]. This is only
relevant for MODE 10 or 11. For MODE 00 with MII bridge port 3, CLK25OUT is available at PDI[6]
anyway. CLK25OUT is not available in MODE 00 if MII bridge port 3 is not configured, CLK25OUT
Enable is ignored.
CLK_25OUT Enable is explained in Table 14.
Table 14: CLK_25OUT Enable
Description
Config
signal
Pin name Register Values
CLK25OUT
Enable
C25_ENA PDI[9]/TX_D[1]/C25_ENA 0x0E00[6]
0 = disable, PDI[6]/CLK25OUT is available for
PDI
1 = enable, PDI[6]/CLK25OUT is 25 MHz clock
output (MODE 10/11 only)
3.2.5 PHY Address Offset
The ET1200 supports two PHY address offset configurations, either 0 or 16. Refer to chapter 4.2 for
details on PHY address configuration.
PHY Address Offset is explained in Table 15.
Table 15: PHY Address Offset
Description Config signal Pin name Register Values
PHY Address Offset PHYAD_OFF PDI[8]/TX_D[0]/PHYAD_OFF 0x0E00[7]
0 = PHY address offset 0
1 = PHY address offset 16
3.2.6 SII EEPROM Size
EEPROM_SIZE determines the size of the EEPROM (and the number of I²C address bytes).
EEPROM_SIZE is sampled at the beginning of the EEPROM access. EEPROM_ SIZE is shown in
Table 16.
Table 16: SII EEPROM Size
Description Config signal Pin name Register Values
EEPROM Size EEPROM_SIZE RUN/EEPROM_SIZE 0x0502[7]
0 = 1 address byte (1 Kbit to 16 Kbit EEPROM)
1 = 2 address bytes (32 Kbit to 4 Mbit EEPROM)