BECKHOFF ET1200 - Manual (Page 48)

PDI Description
III-38 Slave Controller – ET1200 Hardware Description
6.3.11 Timing specifications
Table 42: SPI timing characteristics ET1200
Parameter Min Max Comment
t
CLK
a) 50 ns
b) 166,7 ns
c) 66,7 ns SPI_CLK frequency
a) SPI mode 1/3 with Normal Data Out
Sample or SPI mode 0/1/2/3 with Late
Data Out Sample (f
CLK
≤ 20 MHz)
b) SPI mode 0/2 with Normal Data Out
Sample (f
CLK
≤ 6 MHz)
b) SPI mode 0/2 with Normal Data Out
Sample and Address Extension (f
CLK
≤ 15
MHz)
t
SEL_to_CLK
7 ns First SPI_CLK cycle after SPI_SEL
asserted
t
CLK_to_SEL
a)5 ns
b) t
CLK
/2+5 ns
De-assertion of SPI_SEL after last
SPI_CLK cycle
a) SPI mode 0/2, SPI mode 1/3 with
normal data out sample
b) SPI mode 1/3 with late data out sample
t
read
a) 240 ns
b) 0 ns Only for read access between
address/command and first data byte.
Can be ignored if BUSY or Wait State
Bytes are used.
a) SPI mode 1/3, or SPI mode 0/2 with
Late Data Out Sample
b) SPI mode 0/2 with Normal Data Out
Sample
t
C0_to_BUSY_OE
t
CLK
BUSY OUT Enable assertion after sample
time of last command bit C0.
t
BUSY_valid
15 ns BUSY valid after BUSY OUT Enable
t
SEL_to_DO_valid
15 ns Status/Interrupt Byte 0 bit 7 valid after
SPI_SEL asserted
t
SEL_to_DO_invalid
0 ns Status/Interrupt Byte 0 bit 7 invalid after
SPI_SEL de-asserted
t
STATUS_valid
12 ns Time until status of last access is valid.
Can be ignored if status is not used.
t
access_delay
a) 15 ns
b) 240 ns Delay between SPI accesses
a) typical
b) If last access was shorter than 2 bytes,
otherwise Interrupt Request Register
value I0_[7:0] will not be valid.
t
DI_setup
8 ns SPI_DI valid before SPI_CLK edge
t
DI_hold
3 ns SPI_DI valid after SPI_CLK edge
t
CLK_to_DO_valid
15 ns SPI_DO valid after SPI_CLK edge
t
CLK_to_DO_invalid
0 ns SPI_DO invalid after SPI_CLK edge
t
EEPROM_LOADED_to_acce
ss
300 ns Time between EEPROM_LOADED and
first access
t
IRQ_delay
160 ns Internal delay between AL event and
SPI_IRQ output to enable correct reading
of the interrupt registers.