BECKHOFF ET1200 - Manual (Page 28)

Pin Description
III-18 Slave Controller – ET1200 Hardware Description
3.7.1 MII Interface
LINK_MII(x)
Input signal provided by the PHY if a 100 Mbit/s (Full Duplex) link is established. LINK_MII(x) is active
low.
RX_CLK(x)
MII Receive Clock.
RX_DV(x)
MII receive data valid.
RX_D(x)[3:0]
MII receive data.
RX_ERR(x)
MII receive error.
TX_ENA(x)
MII transmit enable output.
TX_D(x)[3:0]
MII transmit data.
MI_CLK
PHY Management Interface clock.
3.7.1.1 CLK25OUT Signal
CLK25OUT
The ET1200 has to provide an Ethernet PHY with a 25 MHz clock signal (CLK25OUT) if a 25 MHz
crystal is used for clock generation. In case a 25 MHz oscillator is used, CLK25OUT is not necessary,
because the Ethernet PHY and the ET1200 can share the oscillator output. CLK25OUT is not
available at PDI[6]/CLK25OUT in chip mode 00 unless the MII bridge port is configured via SII
EEPROM. With the MII bridge port, CLK25OUT is available regardless of C25ENA. For chip modes
10/11, PDI[7] may be configured to deliver CLK25OUT by pulling up the PDI[9]/TX_D[1]/C25ENA
configuration signal.
CLK25OUT provides a clock signal – if configured – during external or ECAT reset, clock output is
only turned off during power-on reset.
3.7.2 EBUS Interface
The EBUS ports of the ET1200 are open failsafe, i.e., the ET1200 detects if an EBUS port is
unconnected and closes the port internally (no physical link).
EBUS(x)-RX+/EBUS(x)-RX-
EBUS LVDS receive signals. EBUS_RX+ pins incorporate a pull-down resistor R
LI+
and EBUS_RX-
pins incorporate a pull-up resistor R
LI-
, even if the pins are not configured for EBUS.
EBUS(x)-TX+/EBUS(x)-TX-
EBUS LVDS transmit signals.
3.7.3 PDI Pins
PDI[x]
The function of PDI[x] signals depends on the configuration stored in the device SII EEPROM. PDI
signals are not driven (high impedance) until the EEPROM is loaded. This has to be taken into
account especially for Digital Outputs.
PDI signals are not driven (high impedance) if no PDI is configured (PDI Control register
0x0140=0x00).