7 distributed clocks sync/latch signals, 1 signals, 2 timing specifications – BECKHOFF ET1200 User Manual
Page 53: Distributed clocks sync/latch signals, Signals, Timing specifications, Table 44: distributed clocks signals, Figure 19: distributed clocks signals, Figure 20: latchsignal timing, Figure 21: syncsignal timing
Distributed Clocks SYNC/LATCH Signals
Slave Controller
– ET1200 Hardware Description
III-43
7
Distributed Clocks SYNC/LATCH Signals
For details about the Distributed Clocks refer to Section I.
7.1
Signals
The Distributed Clocks unit of the ET1200 has the following external signals (depending on the ESC
configuration):
EtherCAT
device
SYNC/LATCH[1:0]
Figure 19: Distributed Clocks signals
Table 44: Distributed Clocks signals
Signal
Direction
Description
SYNC/LATCH[1:0]
OUT/IN
SyncSignal (OUT) or LatchSignal (IN), direction bitwise
configurable via register 0x0151 / EEPROM.
NOTE: SYNC/LATCH signals are not driven (high impedance) until the EEPROM is loaded.
7.2
Timing specifications
Table 45: DC SYNC/LATCH timing characteristics ET1200
Parameter
Min
Max
Comment
t
DC_LATCH
15 ns
Time between Latch0/1 events
t
DC_SYNC_Jitter
15 ns
SYNC0/1 output jitter
t
DC_SYNC_Pulse_IRQ
40 ns
Pulse length for SYNC0/1 if used as PDI
interrupt in continuous mode
LATCH0/1
t
DC_LATCH
t
DC_LATCH
Figure 20: LatchSignal timing
SYNC0/1
t
DC_SYNC_Jitter
Output event time
t
DC_SYNC_Jitter
Figure 21: SyncSignal timing