Avago Technologies LSI53C1010R - Manual (Page 161)

SCSI Registers 4-43
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
•
A Load and Store instruction is issued with the
memory address mapped to the operating registers of
the chip, not including ROM or RAM.
•
A Load and Store instruction is issued when the
register address is not aligned with the memory
address.
•
A Load and Store instruction is issued with bit 5 in the
DMA Command (DCMD) register cleared or bits 3
or 2 set.
•
A Load and Store instruction is issued when the count
value in the
DMA Byte Counter (DBC) register is not
set at 1, 2, 3, or 4.
•
A Load and Store instruction attempts to cross a
Dword boundary.
•
A Memory Move instruction is executed with one of
the reserved bits in the
DMA Command (DCMD)
register set.
•
A Memory Move instruction is executed with the
source and destination addresses not aligned.
•
A 64-bit Table Indirect Block Move instruction is
executed with a selector index value greater than 0x16.
•
If the Select with ATN/ bit, bit 24, is set for any I/O
instruction other than a Select instruction.