Avago Technologies LSI53C1010R User Manual
Page 387

Index
IX-11
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
command register
commands
configuration info enable (PCICIE)
configuration register read
configuration register write
configuration registers
configuration space
enable read line
error reporting signals
external memory interface timing diagrams
functional description
I/O space
interface control signals
interface signals
interrupt signals
master transaction
master transfer
memory space
performance
system signals
target disconnect
target retry
PERR/
phase mismatch
handling in SCRIPTS
jump address one (PMJAD1)
jump address two (PMJAD2)
jump enable
physical longword address and data
PME
clock (PMEC)
enable (PEN)
status (PST)
support (PMES)
polling
power
and ground signals
management
capabilities
control/status
state
(PWS[1:0])
D0
D1
D2
D3
prefetch
enable (PFEN)
flush
flush (PFF)
SCRIPTS instructions
protocol options
pull disable
pull enable
pull-ups and pull-downs
pull-ups, internal, conditions
R
RAM, See also SCRIPTS RAM
RBIAS
read
line
,
,
line function
modify-write cycles
multiple
,
,
multiple with read line enabled
write instructions
write system memory from a SCRIPT
read/write
instructions
,
system memory from a SCRIPT
receive rate calculation
received
master abort (from master) (RMA)
target abort (from master) (RTA)
register
address
address - A[6:0]
interrupt
map
PCI
SCSI
relative
relative addressing mode
remaining byte count (RBC)
REQ/
REQ/ - GNT/
req/ack offset
REQ64/
request
request 64
reselect
during reselection
instruction
reselected (RSL)
reselection
reserved command
reset
AIP error
AIP sequence value
input
SCSI offset (ROF)
response ID one (RESPID1)
response ID zero (RESPID0)
return instruction
revision ID register