Avago Technologies LSI53C1010R - Manual (Page 338)

6-48 Specifications
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.29 Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte Access Read Cycle
CLK
(Driven by System)
PAR
(Driven by LSI53C1010R
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C1010R
STOP/
(Driven by LSI53C1010R)
DEVSEL/
(Driven by LSI53C1010R)
AD[31:0]
(Driven by LSI53C1010R
C_BE[3:0]/
(Driven by Master)
FRAME/
(Driven by Master)
Master-Addr; Data)
Master-Addr;-Data)
MAD
(Addr Driven by LSI53C1010R
MAS1/
(Driven by LSI53C1010R)
MAS0/
(Driven by LSI53C1010R)
MCE/
(Driven by LSI53C1010R)
MOE/
(Driven by LSI53C1010R)
MWE/
(Driven by LSI53C1010R)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
In
Addr
CMD Byte Enable
In
Data Driven by Memory)
High Order
Address
Order
Address
Middle
Order
Address
Low