Avago Technologies LSI53C1010R - Manual (Page 20)

1-2 Introduction
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
technology detects the SCSI bus configuration and automatically tests
and adjusts the SCSI transfer rate to optimize interoperability. Three levels
of domain validation are provided, assuring robust system operation.
The LSI53C1010R has a local memory bus. This allows local storage of
the device’s BIOS ROM in flash memory or standard EPROMs. The
LSI53C1010R supports programming of local flash memory for BIOS
updates. The chip is packaged in a 456 Ball Grid Array (BGA).
Figure 1.1
shows a typical LSI53C1010R board application connected to external
ROM or flash memory.
Figure 1.1 Typical LSI53C1010R Board Application
LVDlink™ technology is the LSI Logic implementation of Low Voltage
Differential (LVD). LVDlink transceivers allow the LSI53C1010R to
perform either Single-Ended (SE) or LVD transfers. The LSI53C1010R
integrates two high-performance SCSI cores, a 64-bit/66 MHz PCI bus
master DMA core, and the SCSI SCRIPTS processor to meet the
flexibility requirements of Ultra160 SCSI standards. It implements
multithreaded I/O algorithms with minimum processor intervention,
Flash EEPROM
Serial EEPROM
Function A
Serial EEPROM
Function B
Memory Control
Block
LSI53C1010R
64-Bit/66 MHz
PCI to
Dual Channel
Function A
68 Pin
Wide SCSI
Connector
SCSI Data,
Parity, and
Control Signals
SCSI Data,
Parity, and
Control Signals
PCI Interface
PCI Address, Data, Parity
Memory
Address/Data
Bus
A_GPIO/[1:0]
B_GPIO/[1:0]
Ultra160 SCSI
Controller
and
Terminator
Function B
68 Pin
Wide SCSI
Connector
and
Terminator
and Control Signals