Avago Technologies LSI53C1010R - Manual (Page 215)

SCSI Registers 4-97
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
data using programmed I/O. This register can also be
used for diagnostics testing or in the low level mode. The
power-up value of this register is indeterminate.
If the chip is in wide mode ( SCSI Control Three (SCNTL3) ,
bit 3 is set) and SCSI Bus Data Lines (SBDL) is read, both
byte lanes are checked for parity regardless of phase.
When in a nondata phase, this causes a parity error
interrupt to be generated because the upper byte lane
parity in invalid.
Register: 0x5A
Chip Control Two (CCNTL2)
Read/Write
ShSGE Enable Shadowed SGE Register 7
Setting this bit allows access to the SGE Status registers
shadowed behind SIST0 and SIST1.
R Reserved [6:0]
7 6 0
ShSGE R
0 x x x x x x x