Avago Technologies LSI53C1010R - Manual (Page 228)

4-110 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
160 8 0 50.00 10.00 10.00
160 8 1 50.00 10.00 8.00
160 8 2 50.00 10.00 6.67
160 8 3 50.00 10.00 5.71
160 8 4 50.00 10.00 5.00
40 1 0 25.00 20.00 20.00
40 1 1 25.00 20.00 16.00
40 1 2 25.00 20.00 13.33
40 1 3 25.00 20.00 11.43
40 1 4 25.00 20.00 10.00
40 1.5 0 37.50 13.33 13.33
40 1.5 1 37.50 13.33 10.67
40 1.5 2 37.50 13.33 8.89
40 1.5 3 37.50 13.33 7.62
40 1.5 4 37.50 13.33 6.67
40 2 0 50.00 10.00 10.00
40 2 1 50.00 10.00 8.00
40 2 2 50.00 10.00 6.67
40 2 3 50.00 10.00 5.71
40 2 4 50.00 10.00 5.00
40 3 0 75.00 6.67 6.67
40 3 1 75.00 6.67 5.33
40 3 2 75.00 6.67 4.44
40 3 3 75.00 6.67 3.81
40 3 4 75.00 6.67 3.33
40 4 0 100.00 5.00 5.00
40 4 1 100.00 5.00 4.00
40 4 2 100.00 5.00 3.33
40 4 3 100.00 5.00 2.86
Table 4.4 Double Transition Transfer Rates (Cont.)
Clock
(MHz)
Divisor
Number
Xclks
1
Base
Period (ns)
Receive Rate
(Megatransfers/s)
Send Rate
(Megatransfers/s)