Avago Technologies LSI53C1010R - Manual (Page 57)

SCSI Functional Description 2-27
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.2.5.4 Register Considerations
The following is a summary of the registers and bits required to enable
Ultra160 SCSI on the LSI53C1010R device.
•
The PCI Device ID register value must be 0x21.
•
The PCI Max_Lat (ML) register contains a value of 0x12, indicating
it requires the bus every 4.5
µ
s.
•
The SCSI Control Zero (SCNTL0) register:
– Bit 3, EPC (Enable Parity/CRC/AIP Checking) is set to enable
the CRC feature.
– Bit 1, AAP (Assert SATN/ on Parity/CRC/AIP Error), is set in the
initiator mode to assert SATN/ automatically on the detection of
an error.
•
The SCSI Control One (SCNTL1) register:
– Bit 5, DHP (Disable Halt on Parity/CRC/AIP Error or ATN)
(Target Only), is set in accordance with user requirements. When
bit 5 is cleared, a SCSI transfer halts if an error occurs. When
bit 5 is set, a SCSI transfer continues if an error occurs.
•
The SCSI Control Three (SCNTL3) register:
– Bit 7 is now reserved. It was previously the Ultra Enable bit.
– Bits [6:4], SCF[2:0] (Synchronous Clock Conversion Factor),
select the divisor of the SCLK frequency. The SCLK is divided
before its presentation to the synchronous SCSI control logic.
– Bit 3, EWS (Enable Wide SCSI), is set to enable wide SCSI.
Ultra160 requires wide SCSI. Therefore, this bit must be set
during these transfers.
– Bits [2:0] are reserved.
•
The SCSI Transfer (SXFER) register:
– Bits [7:6] are reserved.
– Bits [5:0], MO[5:0] (Max SCSI synchronous offset), are set for
the maximum offset.