Avago Technologies LSI53C1010R - Manual (Page 230)

4-112 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
160 8 1 50.00 5.00 4.00
160 8 2 50.00 5.00 3.33
40 1 0 25.00 10.00 10.00
40 1 1 25.00 10.00 8.00
40 1 2 25.00 10.00 6.67
40 1.5 0 37.50 6.67 6.67
40 1.5 1 37.50 6.67 5.33
40 1.5 2 37.50 6.67 4.44
40 2 0 50.00 5.00 5.00
40 2 1 50.00 5.00 4.00
40 2 2 50.00 5.00 3.33
40 3 0 75.00 3.33 3.33
40 3 1 75.00 3.33 2.67
40 3 2 75.00 3.33 2.22
40 4 0 100.00 2.50 2.50
40 4 1 100.00 2.50 2.00
40 4 2 100.00 2.50 1.67
40 6 0 150.00 1.67 1.67
40 6 1 150.00 1.67 1.33
40 6 2 150.00 1.67 1.11
40 8 0 200.00 1.25 1.25
40 8 1 200.00 1.25 1.00
40 8 2 200.00 1.25 0.83
1. Number Xclks = XCLKS_ST + XCLKH_ST.
Table 4.5 Single Transition Transfer Rates (Cont.)
Clock
(MHz) Divisor Number
Xclks
1
Base
Period
(ns)
Receive Rate
(Megatransfers/s)
Send Rate
(Megatransfers/s)