Avago Technologies LSI53C1010R - Manual (Page 331)

PCI and External Memory Interface Timing Diagrams 6-41
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Table 6.32 External Memory Write
Symbol Parameter Min Max Min Max Unit
t
1
Shared signal input setup time 3 – 7 – ns
t
2
Shared signal input hold time 0 – 0 – ns
t
3
CLK to shared signal output valid 2 6 2 11 ns
t
11
Address setup to MAS/ HIGH 25 – 25 – ns
t
12
Address hold from MAS/ HIGH 15 – 15 – ns
t
13
MAS/ pulse width 25 – 25 – ns
t
20
Data setup to MWE/ LOW 30 – 30 – ns
t
21
Data hold from MWE/ HIGH 20 – 20 – ns
t
22
MWE/ pulse width 100 – 100 – ns
t
23
Address setup to MWE/ LOW 60 – 60 – ns
t
24
MCE/ LOW to MWE/ HIGH 120 – 120 – ns
t
25
MCE/ LOW to MWE/ LOW 25 – 25 – ns
t
26
MWE/ HIGH to MCE/ HIGH 25 – 25 – ns