Dma fifo byte count (dfbc), Registers: 0xe8–0xef, Registers: 0xf0–0xf1 – Avago Technologies LSI53C1010R User Manual
Page 242: Registers: 0xf2–0xf3
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Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
If CRCDSEL = 0b11, this register contains the saved bad
CRC value that was calculated when a CRC error was
detected. After a CRC error is detected, this register is
not overwritten until the error condition is cleared.
Registers: 0xE8–0xEF
Reserved
This register is reserved.
Registers: 0xF0–0xF1
DMA FIFO Byte Count (DFBC)
Read Only
DFBC
DMA FIFO Byte Count
[15:0]
This 16-bit read only register contains the actual number
of bytes contained in the DMA FIFO. This register is not
stable while data is being transferred. This register can
be used during error recovery.
Registers: 0xF2–0xF3
Reserved
This register is reserved.
31
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
0
DFBC
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
15
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0