Avago Technologies LSI53C1010R - Manual (Page 260)

5-12 SCSI SCRIPTS Instruction Set
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
register controls whether the LSI53C1010R halts on
these conditions immediately, or waits until completion of
the current Move.
Initiator Mode
The LSI53C1010R verifies that it is connected to the
SCSI bus as an initiator before executing this instruction.
The LSI53C1010R waits for an unserviced phase to
occur. An unserviced phase is defined as any phase
(with SREQ/ asserted) for which the LSI53C1010R has
not yet transferred data by responding with a SACK/.
The LSI53C1010R compares the SCSI phase bits in the
DMA Command (DCMD) register with the latched SCSI
phase lines stored in the SCSI Status One (SSTAT1)
register. These phase lines are latched when SREQ/ is
asserted.
OPC Instruction Defined
0 CHMOV/CHMOV64
1 MOVE/MOVE64