Avago Technologies LSI53C1010R - Manual (Page 366)

A-2 Register Summary
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Latency Timer (LT) 0x0D Read/Write 4-8
Max_Lat (ML) 0x3F Read Only 4-17
Min_Gnt (MG) 0x3E Read Only 4-17
Next Item Pointer (NIP) 0x41 Read Only 4-18
Power Management Capabilities (PMC) 0x42–0x43 Read Only 4-19
Power Management Control/Status (PMCSR) 0x44–0x45 Read/Write 4-20
Reserved 0x0F – 4-9
Reserved 0x24–0x27 – 4-11
Reserved 0x28–0x2B – 4-11
Reserved 0x35–0x37 – 4-15
Reserved 0x38–0x3B – 4-15
Revision ID (RID) 0x08 Read Only 4-6
Status 0x06–0x07 Read/Write 4-5
Subsystem ID (SID) 0x2E–0x2F Read Only 4-13
Subsystem Vendor ID (SVID) 0x2C–0x2D Read Only 4-12
Vendor ID 0x00–0x01 Read Only 4-2
Table A.1 LSI53C1010R PCI Register Map (Cont.)
Register Name Address Read/Write Page