Avago Technologies LSI53C1010R - Manual (Page 308)

6-18 Specifications
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.14 Operating Register/SCRIPTS RAM Read, 64 Bits
Table 6.20 Operating Register/SCRIPTS RAM Read, 64 Bits
Symbol Parameter
66 MHz PCI 33 MHz PCI
Unit Min Max Min Max
t
1
Shared signal input setup time 3 – 7 – ns
t
2
Shared signal input hold time 0 – 0 – ns
t
3
CLK to shared signal output valid 2 6 2 11 ns
Data
Byte Enable
t
2
t
1
t
2
t
1
t
2
t
2
t
2
t
3
t
2
t
1
t
3
CLK
(Driven by System)
FRAME/
(Driven by Master)
AD[31:0]
(Driven by Master-Addr;
C_BE[3:0]/
(Driven by Master)
PAR; PAR64
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C1010R)
STOP/
(Driven by LSI53C1010R)
DEVSEL/
(Driven by LSI53C1010R)
Out
t
3
In Out
t
3
LSI53C1010R-Data)
LSI53C1010R-Data)
t
1
t
2
Addr
Lo
Addr
Hi
t
1
Dual
Addr
t
1
AD[63:32]
(Driven by Master-Addr;
LSI53C1010R-Data)
Hi Addr
t
2
Byte Enable
t
2
C_BE[7:4]/
(Driven by Master)
t
1
Bus CMD
t
1
t
1
t
2
Bus
CMD
In
t
3
REQ64/
(Driven by Master)
ACK64/
(Driven by LSI53C1010R)
t
1
Data
Byte Enable
t
2
t
1
t
2
t
1
t
2
t
2
t
2
t
3
t
2
t
1
t
3
Out
t
3
In Out
t
3
t
1
t
2
Addr
Lo
Addr
Hi
t
1
Dual
Addr
t
1
Hi Addr
t
2
Byte Enable
t
2
t
1
Bus CMD
t
1
t
1
t
2
Bus
CMD
In
t
3
t
1