Document Outline

• E Series User Manual
• Support
  • Worldwide Technical Support and Product Information
  • National Instruments Corporate Headquarters
  • Worldwide Offices
• Important Information
  • Warranty
  • Copyright
  • Trademarks
  • Patents
  • WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS
• Contents
• About This Manual
• Chapter 1 DAQ System Overview
  • Figure 1-1. DAQ System Overview
  • DAQ Hardware
    • DAQ-STC
    • Calibration Circuitry
      • Internal or Self-Calibration
      • External Calibration
  • Signal Conditioning
    • Sensors and Transducers
    • Signal Conditioning Options
      • SCXI
      • SCC
      • 5B Series
  • Cables and Accessories
    • Using Accessories with Devices
      • Table 1-1. 68-Pin and DAQCard E Series Accessories and Recommended Cables
      • Table 1-2. 100-Pin E Series Accessories and Recommended Cables
      • Table 1-3. E Series DAQ Accessories Overview
    • Custom Cabling
  • Programming Devices in Software
  • I/O Connector Signal Descriptions
    • Table 1-4. I/O Connector Signal Descriptions
  • Terminal Name Equivalents
    • Table 1-5. Terminal Name Equivalents
  • +5 V Power Source
• Chapter 2 Analog Input
  • Figure 2-1. Analog Input Circuitry Block Diagram
  • Analog Input Circuitry
    • Mux
    • Instrumentation Amplifier (NI-PGIA)
    • A/D Converter
    • AI FIFO
    • Analog Trigger
    • AI Timing Signals
  • Input Polarity and Range
    • Table 2-1. Input Ranges for NI 6020E, NI 6040E, NI 6052E, NI 6062E, and NI 6070E/6071E
    • Table 2-2. Input Ranges for NI 6011E and NI 6030E/6031E/6032E/6033E
    • Table 2-3. Input Ranges for NI 6023E/6024E/6025E and NI 6034E/6035E/6036E
  • Analog Input Terminal Configuration
    • Table 2-4. Analog Input Terminal Configuration
    • Figure 2-2. E Series PGIA
    • Table 2-5. NI-PGIA Signal
  • Dither
    • Figure 2-3. Dither
  • Multichannel Scanning Considerations
    • Use Low Impedance Sources
    • Use Short High-Quality Cabling
    • Carefully Choose the Channel Scanning Order
      • Avoid Switching from a Large to a Small Input Range
      • Insert Grounded Channel between Signal Channels
      • Minimize Voltage Step between Adjacent Channels
    • Avoid Scanning Faster than Necessary
      • Example 1
      • Example 2
    • AI Data Acquisition Methods
      • Software-Timed Acquisitions
      • Hardware-Timed Acquisitions
  • Analog Input Triggering
    • AI Start Trigger Signal
      • Using a Digital Source
      • Figure 2-4. ai/StartTrigger Source Timing Requirements
      • Using an Analog Source
    • Outputting the AI Start Trigger Signal
      • Figure 2-5. PFI 0/AI START TRIG Timing Behavior
    • AI Reference Trigger Signal
      • Figure 2-6. Reference Trigger Final Buffer
      • Using a Digital Source
      • Figure 2-7. ai/ReferenceTrigger Source Timing Requirements
      • Using an Analog Source
      • Outputting the AI Reference Trigger Signal
      • Figure 2-8. PFI 1/AI REF TRIG Timing Behavior
    • AI Pause Trigger Signal
      • Using a Digital Source
      • Using an Analog Source
  • Connecting Analog Input Signals
    • Table 2-6. Recommended Input Configurations
    • Types of Signal Sources
      • Floating Signal Sources
      • Ground-Referenced Signal Sources
  • Differential Connection Considerations
    • Differential Connections for Ground-Referenced Signal Sources
      • Figure 2-9. Differential Connections for Ground-Referenced Signal Sources
      • Common-Mode Signal Rejection Considerations
    • Differential Connections for Non-Referenced or Floating Signal Sources
      • Figure 2-10. Connecting a Floating Signal Source to a DIFF Mode Channel
  • Single-Ended Connection Considerations
    • Common-Mode Signal Rejection Considerations
    • Single-Ended Connections for Floating Signal Sources (RSE Configuration)
      • Figure 2-11. Single-Ended Connections for Floating Signal Sources (RSE Configuration)
    • Single-Ended Connections for Grounded Signal Sources (NRSE Configuration)
      • Figure 2-12. Single-Ended Connections for Grounded Signal Sources (NRSE Configuration)
  • Field Wiring Considerations
  • Configuring AI Modes in Software
    • Traditional NI-DAQ (Legacy)
      • Figure 2-13. AI Config VI
    • NI-DAQmx
      • Figure 2-14. NI-DAQmx Create Virtual Channel.vi
  • Analog Input Timing Signals
    • Figure 2-15. Analog Input Timing Engine Clock Routing and Timing Options.
    • Figure 2-16. Interval Sample
    • Figure 2-17. Typical Posttrigger Acquisition
    • Figure 2-18. Typical Pretrigger Acquisition
    • AI Start Trigger Signal
      • Using a Digital Source
      • Figure 2-19. ai/StartTrigger Timing Requirements
      • Using an Analog Source
      • Outputting the AI Start Trigger Signal
      • Figure 2-20. PFI 0/AI START TRIG Timing Behavior
    • AI Reference Trigger Signal
      • Figure 2-21. Reference Trigger Final Buffer
      • Using a Digital Source
      • Figure 2-22. ai/ReferenceTrigger Source Timing Requirements
      • Using an Analog Source
      • Outputting the AI Reference Trigger Signal
      • Figure 2-23. PFI 1/AI REF TRIG Timing Behavior
    • AI Pause Trigger Signal
      • Using a Digital Source
      • Using an Analog Source
    • AI Sample Clock Signal
      • Using an Internal Source
      • Using an External Source
      • Figure 2-24. ai/SampleClock Timing Requirements
      • Outputting the AI Sample Clock Signal
      • Figure 2-25. ai/SampleClock Input
      • Figure 2-26. ai/SampleClock Output
      • Other Timing Requirements
      • Figure 2-27. ai/SampleClock and ai/StartTrigger
    • AI Sample Clock Timebase Signal
      • Figure 2-28. ai/SampleClockTimebase Timing Requirements
    • AI Convert Clock Signal
      • Using an Internal Source
      • Using an External Source
      • Figure 2-29. ai/ConvertClock Source Timing Requirements
      • Outputting the AI Convert Clock Signal
      • Figure 2-30. PFI 2/AI CONV CLK Timing Behavior
      • Using a Delay from Sample Clock to Convert Clock
      • Figure 2-31. ai/SampleClock and ai/ConvertClock
      • Other Timing Requirements
      • Figure 2-32. ai/SampleClock and ai/ConvertClock Signals
    • AI Convert Clock Timebase Signal
    • Master Timebase Signal
      • Figure 2-33. MasterTimebase Timing Requirements
    • AI Hold Complete Event Signal
      • Figure 2-34. ai/HoldCompleteEvent Timing
    • External Strobe Signal
      • Figure 2-35. External Strobe Timing
  • Getting Started with AI Applications in Software
• Chapter 3 Analog Output
  • Figure 3-1. Analog Output Block Diagram
  • Analog Output Circuitry
    • DACs
    • DAC FIFO
    • AO Sample Clock
    • Polarity and Reference Selection
      • Table 3-1. Polarity and Reference Range
  • Reference Selection
  • Polarity Selection
  • Reglitch Selection
  • Minimizing Glitches on the Output Signal
  • AO Data Generation Methods
    • Software-Timed Generations
    • Hardware-Timed Generations
      • Buffered
      • Non-Buffered
  • Analog Output Triggering
    • AO Start Trigger Signal
      • Using a Digital Source
      • Figure 3-2. ao/StartTrigger Digital Source Timing Requirements
      • Using an Analog Source
      • Outputting the AO Start Trigger Signal
      • Figure 3-3. PFI 6/AO START TRIG Timing Behavior
    • AO Pause Trigger Signal
      • Using a Digital Source
      • Using an Analog Source
  • Connecting Analog Output Signals
    • Figure 3-4. Analog Output Connections
  • Waveform Generation Timing Signals
    • Figure 3-5. Analog Output Timing Engine
    • AO Start Trigger Signal
      • Using a Digital Source
      • Figure 3-6. ao/StartTrigger Digital Source Timing Requirements
      • Using an Analog Source
      • Outputting the AO Start Trigger Signal
      • Figure 3-7. PFI 6/AO START TRIG Timing Behavior
    • AO Pause Trigger Signal
      • Using a Digital Source
      • Using an Analog Source
    • AO Sample Clock Signal
      • Using an Internal Source
      • Using an External Source
      • Figure 3-8. ao/SampleClock Source Timing Requirements
      • Outputting the AO Sample Clock Signal
      • Figure 3-9. PFI 5/AO SAMP CLK Timing Behavior
      • Other Timing Requirements
      • Figure 3-10. ao/SampleClock and ao/StartTrigger
    • AO Sample Clock Timebase Signal
      • Figure 3-11. ao/SampleClockTimebase Signal Timing Requirements
    • Master Timebase Signal
      • Figure 3-12. MasterTimebase Timing Requirements
  • Getting Started with AO Applications in Software
• Chapter 4 Digital I/O
  • Figure 4-1. DIO Circuitry Block Diagram
  • Extended Digital I/O
    • Port 3 Signal Assignments
      • Table 4-1. Configuration Terminology and Signal Assignments
    • Power-On State
      • Changing DIO Power-On State to Pulled Low
      • Figure 4-2. DIO Configuration for High DIO Power-On State
    • Timing Specifications
      • Table 4-2. Signal Descriptions
    • Mode 1 Input Timing
      • Figure 4-3. Input Transfer in Mode 1 Timing Specifications
      • Table 4-3. Input Transfer in Mode 1 Timing Specifications
    • Mode 1 Output Timing
      • Figure 4-4. Output Transfer in Mode 1 Timing Specifications
      • Table 4-4. Output Transfer in Mode 1 Timing Specifications
    • Mode 2 Bidirectional Timing
      • Figure 4-5. Bidirectional Transfer Timing Specifications
      • Table 4-5. Bidirectional Transfer Timing Specification
  • Power-On States of the PFI and DIO Lines
  • Connecting Digital I/O Signals
    • Figure 4-6. P0.<0..3> Configured for Digital Input, P0.<4..7> Configured for Digital Output
  • Getting Started with DIO Applications in Software
• Chapter 5 Counters
  • Figure 5-1. Counter Block Diagram
  • Counter Triggering
    • Start Trigger
    • Pause Trigger
  • Counter Timing Signals
    • Figure 5-2. Counter Timing Signals
    • Counter 0 Source Signal
      • Figure 5-3. Ctr0Source Timing Requirements
    • Counter 0 Gate Signal
      • Figure 5-4. Ctr0Gate Timing Requirements
    • Counter 0 Internal Output Signal
      • Figure 5-5. Ctr0InternalOutput Signal Behavior
      • CTR 0 OUT Pin
      • Figure 5-6. CTR 0 OUT and Ctr0InternalOutput
    • Counter 0 Up/Down Signal
    • Counter 1 Source Signal
      • Figure 5-7. Ctr1Source Signal Timing Requirements
    • Counter 1 Gate Signal
      • Figure 5-8. Ctr1Gate Signal Timing Requirements
    • Counter 1 Internal Output Signal
      • Figure 5-9. Ctr1InternalOutput Signal Behavior
    • Counter 1 Up/Down Signal
    • Frequency Output Signal
    • Master Timebase Signal
      • Figure 5-10. MasterTimebase Timing Requirements
  • Getting Started with Counter Applications in Software
• Chapter 6 Programmable Function Interfaces (PFI)
  • Inputs
  • Outputs
• Chapter 7 Digital Routing
  • Timing Signal Routing
    • Figure 7-1. ai/ConvertClock Signal Routing
  • Connecting Timing Signals
    • Figure 7-2. Connecting Timing Signals
  • Routing Signals in Software
    • Table 7-1. Functions For Routing Signals.
• Chapter 8 Real-Time System Integration Bus (RTSI)
  • RTSI Triggers
    • PCI E Series Devices
      • Figure 8-1. PCI E Series Signal Connection Scheme
    • PXI E Series Devices
      • Figure 8-2. PXI E Series Signal Connection Scheme
  • Device and RTSI Clocks
  • Synchronizing Multiple Devices
• Chapter 9 Bus Interface
  • MITE and DAQPnP
  • Using PXI with CompactPCI
  • Data Transfer Methods
    • Direct Memory Access (DMA)
    • Interrupt Request (IRQ)
    • Programmed I/O
    • Changing Data Transfer Methods between DMA and IRQ
• Chapter 10 Triggering
  • Triggering with a Digital Source
    • Figure 10-1. Falling-Edge Trigger
  • Triggering with an Analog Source
    • Figure 10-2. Analog Trigger Circuit
    • PFI 0/AI START TRIG Pin
    • Analog Input Channel
    • Analog Trigger Actions
  • Analog Trigger Types
    • Level Triggering
      • Figure 10-3. Below-Level Analog Triggering Mode
      • Figure 10-4. Above-Level Analog Triggering Mode
    • Level Triggering with Hysteresis
      • Figure 10-5. High Hysteresis
      • Figure 10-6. Low Hysteresis
    • Window Triggering
      • Figure 10-7. Window Triggering
  • Analog Trigger Accuracy
• Appendix A Device-Specific Information
  • Figure A-1. NI 6011E (NI PCI-MIO-16XE-50) Block Diagram
  • Figure A-2. NI 6011E (NI PCI-MIO-16XE-50) Pinout
  • Figure A-3. NI 6013/6014 Block Diagram
  • Figure A-4. NI 6013 Pinout
  • Figure A-5. NI 6014 Pinout
  • Table A-1. NI DAQPad-6015/6016 Versions
  • Figure A-6. DAQPad-6015/6016 Block Diagram
  • Figure A-7. BNC DAQPads Front Panel
  • Figure A-8. BNC DAQPad Analog Input Circuitry
  • Figure A-9. BNC DACPads Single-Ended Connections
  • Figure A-10. BNC DAQPads Analog Output Circuitry
  • Figure A-11. Counter 0 Out
  • Figure A-12. PFI 0/AI Start Trigger
  • Figure A-13. User <1..2> BNC Connection
  • Figure A-14. BNC User <1..2> Example
  • Figure A-15. Removing the BNC DAQPad Combicons
  • Table A-2. LEDs Behavior
  • Figure A-16. DAQPad-6015/6016 Fuse Removal
  • Figure A-17. DAQPad-6015 Mass Termination Device
  • Figure A-18. NI DAQPad-6015 Pinout
  • Figure A-19. NI DAQPad-6015 BNC Device Pinout
  • Figure A-20. NI DAQPad-6015 Mass Termination Pinout
  • Figure A-21. NI DAQPad-6016 Pinout
  • Table A-3. DAQPad-6020E Versions
  • Figure A-22. DAQPad-6020E Block Diagram
  • Figure A-23. BNC DAQPad Front Panel
  • Figure A-24. BNC DAQPads Analog Input Circuitry
  • Figure A-25. BNC Single-Ended Signals
  • Figure A-26. Analog Output
  • Figure A-27. AO EXT REF
  • Figure A-28. Counter 0 Out
  • Figure A-29. PFI 0/AI Start Trigger
  • Figure A-30. BNC User <1..2> Connection
  • Figure A-31. BNC User <1..2> Example
  • Figure A-32. Removing the BNC DAQPad Device Combicons
  • Table A-4. DAQPad-6020E LEDs
  • Figure A-33. NI DAQPad-6020E Pinout
  • Figure A-34. NI DAQPad-6020E BNC Pinout
  • Figure A-35. NI PCI-6023E/6024E/6025E and NI PXI-6025E Block Diagram
  • Figure A-36. DAQCard-6024E Block Diagram
  • Figure A-37. NI 6023E Pinout
  • Figure A-38. NI 6024E Pinout
  • Figure A-39. NI 6025E Pinout
  • Figure A-40. NI 6030E/6031E Block Diagram
  • Figure A-41. NI 6032E/6033E Block Diagram
  • Figure A-42. NI 6030E Pinout
  • Figure A-43. NI PCI-MIO-16XE-10 (NI 6030E) Pinout
  • Figure A-44. NI 6031E Pinout
  • Figure A-45. NI 6032E Pinout
  • Figure A-46. NI 6033E Pinout
  • Figure A-47. NI PCI-6034E/6035E/6036E Block Diagram
  • Figure A-48. DAQCard-6036E Block Diagram
  • Figure A-49. NI 6034E Pinout
  • Figure A-50. NI 6035E Pinout
  • Figure A-51. NI 6036E Pinout
  • Figure A-52. NI PXI-6040E Block Diagram
  • Figure A-53. NI 6040E Pinout
  • Figure A-54. PCI-MIO-16E-4 Block Diagram
  • Figure A-55. NI PCI-MIO-16E-4 (NI 6040E) Pinout
  • Table A-5. NI DAQPad-6052E Versions
  • Figure A-56. DAQPad-6052E Block Diagram
  • Figure A-57. BNC DAQPad Front Panel
  • Figure A-58. Analog Input Circuitry
  • Figure A-59. Single-Ended Signals
  • Figure A-60. Analog Output Circuitry
  • Figure A-61. AO EXT REF
  • Figure A-62. Counter 0 Out
  • Figure A-63. PFI 0/AI Start Trigger
  • Figure A-64. User <1..2> BNCs
  • Figure A-65. User <1..2> BNC Example
  • Figure A-66. Removing the BNC Combicon
  • Table A-6. DAQPad-6052E LEDs
  • Figure A-67. NI DAQPad-6052E Pinout
  • Figure A-68. NI DAQPad-6052E BNC Device Pinout
  • Figure A-69. NI PCI/PXI-6052E Block Diagram
  • Figure A-70. NI PCI/PXI-6052E Pinout
  • Figure A-71. DAQCard-6062E Block Diagram
  • Figure A-72. NI 6062E Pinout
  • Table A-7. NI DAQPad-6070E Versions
  • Figure A-73. DAQPad-6070E Block Diagram
  • Figure A-74. BNC DAQPad Front Panel
  • Figure A-75. Analog Input Circuitry
  • Figure A-76. Single-Ended Channel
  • Figure A-77. Analog Output
  • Figure A-78. AO EXT REF
  • Figure A-79. Counter 0 Out
  • Figure A-80. PFI 0/AI Start Trigger
  • Figure A-81. User <1..2> BNCs
  • Figure A-82. User <1..2> BNC Example
  • Figure A-83. Removing the BNC Combicon
  • Table A-8. DAQPad-6070E LEDs
  • Figure A-84. NI DAQPad-6070E BNC Pinout
  • Figure A-85. NI 6070E/6071E Block Diagram
  • Figure A-86. NI PCI/PXI-6070E Pinout
  • Figure A-87. NI PCI-6071E Pinout
  • Figure A-88. PCI-MIO-16E-1 Block Diagram
  • Figure A-89. NI PCI-MIO-16E-1 (NI 6070E) Pinout
• Appendix B I/O Connector Pinouts
  • Table B-1. E Series I/O Connector Pinouts
  • Figure B-1. 100-68-68-Pin Extended AI I/O Connector Pinout
  • Figure B-2. 100-68-68-Pin Extended DIO I/O Connector Pinout
  • Figure B-3. 100-50-50-Pin Extended DIO I/O Connector Pinout
  • Figure B-4. 50-Pin MIO I/O Connector Pinout
• Appendix C Troubleshooting
  • Figure C-1. Interval Sample
• Appendix D Technical Support and Professional Services
• Glossary
  • Symbols
  • A
  • B-C
  • D-F
  • H-N
  • O-R
  • S-T
  • V
• Index
  • Numerics
  • A-B
  • C-D
  • E-M
  • N
  • O-P
  • R-T
  • U-W