National Instruments Data Acquisition Device E Series - Manual (Page 179)

Appendix A Device-Specific Information
E Series User Manual A-44 ni.com
NI 6030E/6031E/6032E/6033E Dither
You cannot disable dither on the NI 6030E/6031E/6032E/6033E. The ADC
resolution is so fine that the ADC and the PGIA inherently produce almost
0.5 LSB
rms
of noise. This configuration is equivalent to having a dither
circuit that is always enabled.
NI 6030E/6031E/6032E/6033E Block Diagrams
Figure A-40 shows a block diagram of the NI 6030E/6031E.
Figure A-40. NI 6030E/6031E Block Diagram
PCI/PXI Bus
Configuration
Memory
Timing
PFI / Trigger
I/O Connector
3
2
2
Digital I/O (8)
12-Bit
Sampling
A/D
Converter
REF
Buffer
Programmable
Gain
Amplifier
–
Calibration
Mux
Mux Mode
Selection
Switches
Voltage
REF
Calibration
DACs
4
Calibration
DACs
DAC0
DAC1
DAQ - STC
Analog Input
Timing/Control
Analog Output
Timing/Control
Digital I/O
Trigger
Counter/
Timing I/O
RTSI Bus
Interface
DMA/
Interrupt
Request
Bus
Interface
(8)*
(8)*
AI Control
IRQ
DMA
AO Control
Data (16)
Trigger Level
DACs
Analog
Trigger
Circuitry
Data (16)
Trigger
EEPROM
Address/Data
Control
Data (16)
Analog
Input
Control
EEPROM
Control
DMA
Interface
MIO
Interface
DAQ-STC
Bus
Interface
Analog
Output
Control
I/O
Bus
Interface
Address (5)
Analog
Muxes
DAC
FIFO
ADC
FIFO
MITE
Generic
Bus
Interface
PCI
Bus
Interface
+
RTSI
Data (16)