Altera Internal Memory (RAM and ROM) IP Core - Manual (Page 11)

Embedded Memory Functional Description
3
2014.12.17
UG-01068 Subscribe
Send Feedback
Describes the features and functionality of the embedded memory blocks and the ports of the RAM: 1-
PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT IP cores.
Memory Block Types
Altera provides various sizes of embedded memory blocks for various devices.
The parameter editor allows you to implement your memory in the following ways:
• Select the type of memory blocks available based on your target device. To select the appropriate
memory block type for your device, obtain more information about the features of your selected
embedded memory block in your target device, such as the maximum performance, supported
configurations (depth × width), byte enable, power-up condition, and the write and read operation
triggering.
• Use logic cells. As compared to embedded memory resources, using logic cells to create memory
reduces the design performance and utilizes more area. This implementation is normally used when
you have used up all the embedded memory resources. When logic cells are used, the parameter editor
provides you with the following two types of logic cell implementations:
• Default logic cell style—the write operation triggers (internally) on the rising edge of the write clock
and have continuous read. This implementation uses less logic cells and is faster, but it is not fully
compatible with the Stratix M512 emulation style.
• Stratix M512 emulation logic cell style—the write operation triggers (internally) on the falling edge
of the write clock and performs read only on the rising edge of the read clock.
• Select the Auto option, which allows the software to automatically select the appropriate embedded
memory resource. When you set the memory block type to Auto, the compiler favors larger block
types that can support the memory capacity you require in a single embedded memory block. This
setting gives the best performance and requires no logic elements (LEs) for glue logic. When you create
the memory with specific embedded memory blocks, such as M9K, the compiler is still able to emulate
wider and deeper memories than the block type supported natively. The compiler spans multiple
embedded memory blocks (only of the same type) with glue logic added in the LEs as needed.
Note: To obtain proper implementation based on the memory configuration you set, allow the Quartus II
software to automatically choose the memory type. This gives the compiler the flexibility to place
the memory function in any available memory resources based on the functionality and size.
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134