Altera Internal Memory (RAM and ROM) IP Core - Manual (Page 38)

Parameter Legal Values Description
More Options
When you select
With one read port
and one write port,
the following option
is available:
• Use clock enable
for write input
registers
When you select
With two read /
write ports, the
following options are
available:
• Use clock enable
for port A input
registers
• Use clock enable
for port B input
registers
• Use clock enable
for port A output
registers
• Use clock enable
for port B output
register
On/Off Clock enable for port B input
and output registers are
turned on by default. You
only need to specify whether
to use clock enable for port A
input and output registers.
UG-01068
2014.12.17
RAM: 2-Port IP Core Parameters 4-13
Embedded Memory Signals and Parameters Altera Corporation
Send Feedback