Altera Internal Memory (RAM and ROM) IP Core - Manual (Page 46)

Parameter Legal Values Description
More Options
Use clock enable for
port A input
registers
On/Off Specifies whether to use
clock enable for port A input
registers.
Use clock enable for
port A output
registers
On/Off Specifies whether to use
clock enable for port A
output registers.
Create an
‘addressstall_a’ input
port.
On/Off Specifies whether to create
addressstall_a and address‐
stall_b input ports. You can
create these ports to act as an
extra active low clock enable
input for the address
registers.
Create an
‘addressstall_b’ input
port.
On/Off Specifies whether to create
an asynchronous clear port
for the registered ports.
Create an ‘aclr’ asynchronous clear for the
registered ports.
On/Off Specifies whether to create
an asynchronous clear port
for the registered ports.
More Options
‘q_a’ port On/Off Specifies whether the ‘q_a’
port should be cleared by the
aclr port.
‘q_b’ port On/Off Specifies whether the ‘q_b’
port should be cleared by the
aclr port.
Parameter Settings: Mem Init
Do you want to specify the initial content of the
memory?
Yes, use this file for
the memory content
data
Specifies the initial content
of the memory.
In ROM mode you must
specify a memory initializa‐
tion file (.mif) or a hexadec‐
imal (Intel-format) file (.hex)
.
The Yes, use this file for the
memory content data
option is turned on by
default.
The initial content file should conform to which
port’s dimensions?
• PORT_A
• PORT_B
Specifies whether the initial
content file conforms to port
A or port B.
UG-01068
2014.12.17
ROM: 2-PORT IP Core Parameters 4-21
Embedded Memory Signals and Parameters Altera Corporation
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