Altera Internal Memory (RAM and ROM) IP Core - Manual (Page 34)

RAM: 2-Port IP Core Parameters
This table lists the parameters for the RAM: 2-Port IP Core
Table 4-3: RAM: 2-Port Parameter Settings
Parameter Legal Values Description
Parameter Settings: General
How will you be using the dual port RAM?
• With one read
port and one
write port
• With two read /
write ports
Specifies how you use the
dual port RAM.
How do you want to specify the memory size?
• As a number of
words
• As a number of
bits
Determines whether to
specify the memory size in
words or bits.
Parameter Settings: Widths/ Blk Type
How many <X>-bit words of memory?
— Specifies the number of <X>-
bit words.
Use different data widths on different ports On/Off Specifies whether to use
different data widths on
different ports.
When you select With one read port and one write
port, the following options are available:
• How wide should the ‘q_a’ output bus be?
• How wide should the ‘data_a’ input bus be?
• How wide should the ‘q’ output bus be?
—
Specifies the width of the
input and output ports.
When you select With two read/write ports, the
following options are available:
• How wide should the ‘q_a’ output bus be?
• How wide should the ‘q_b’ output bus be?
What should the memory block type be?
Auto, M-RAM,
M4K, M512, M9K,
M10K, M144K,
MLAB, M20K, LCs
Specifies the memory block
type. The types of memory
block that are available for
selection depends on your
target device.
How should the memory be implemented?
• Use default logic
cell style
• Use Stratix M512
emulation logic
cell style
Specifies the logic cell
implementation options.
This option is enabled only
when you choose LCs
memory type.
UG-01068
2014.12.17
RAM: 2-Port IP Core Parameters 4-9
Embedded Memory Signals and Parameters Altera Corporation
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