Altera Stratix IV E FPGA Development Board User Manual

Page 18

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2–10

Chapter 2: Board Components

MAX II CPLD EPM2210 System Controller

Stratix IV E FPGA Development Board Reference Manual

May 2011

Altera Corporation

FSM_D18

2.5-V

P14

B26

U3.E1

FSM bus data

FSM_D19

2.5-V

R7

J22

U3.E2

FSM bus data

FSM_D20

2.5-V

P8

J21

U3.F1

FSM bus data

FSM_D21

2.5-V

T7

C24

U3.F2

FSM bus data

FSM_D22

2.5-V

N8

E25

U3.G1

FSM bus data

FSM_D23

2.5-V

R8

D25

U3.G2

FSM bus data

FSM_D24

2.5-V

F12

D24

U3.J1

FSM bus data

FSM_D25

2.5-V

D16

A27

U3.J2

FSM bus data

FSM_D26

2.5-V

F13

A29

U3.K1

FSM bus data

FSM_D27

2.5-V

D15

C27

U3.K2

FSM bus data

FSM_D28

2.5-V

F14

C28

U3.L1

FSM bus data

FSM_D29

2.5-V

D14

E23

U3.L2

FSM bus data

FSM_D30

2.5-V

E12

D23

U3.M1

FSM bus data

FSM_D31

2.5-V

C15

B28

U3.M2

FSM bus data

HSMA_PSNTn

2.5-V

F16

J19.160, R189

HSMC port A present

HSMB_PSNTn

2.5-V

G13

J9.160, R189

HSMC port B present

JTAG_EPM2210_TDO

2.5-V

M5

U35.5

JTAG data output for MAX II

JTAG_FPGA_TDO

2.5-V

L6

G29

U35.2

JTAG data output for FPGA

JTAG_TCK

2.5-V

P3

F30

J24.1, U8.L9,

J9.35, J19.35

JTAG clock signal

JTAG_TMS

2.5-V

N4

H28

J24.5, U8.J11,

J9.36, J19.36

JTAG mode select signal

MAX_CLK

2.5-V

H5

N3

FSM bus MAX II clock

MAX_CSn

2.5-V

L16

N29

FSM bus MAX II chip select

MAX_DIP0

2.5-V

E14

SW2.1

DIP - reserved

MAX_DIP1

2.5-V

D13

SW2.2

DIP - reserved

MAX_DIP2

2.5-V

K16

SW2.3

DIP - reserved

MAX_DIP3

2.5-V

N2

SW2.4

DIP - reserved

MAX_DIP4

2.5-V

N14

SW2.5

DIP - reserved

MAX_DIP5

2.5-V

M13

SW2.6

DIP - reserved

MAX_DIP6

2.5-V

N15

SW2.7

DIP - reserved

MAX_EMB

2.5-V

E15

D15

User-defined push-button switch
(labeled as USER_1 on the board)

MAX_ERROR

2.5-V

H15

D20

FPGA configuration error LED

MAX_FACTORY

2.5-V

G16

D18

FPGA factory configuration LED

MAX_LOAD

2.5-V

H14

D17

FPGA configuration active LED

MAX_OEn

2.5-V

K13

K27

FSM bus MAX II output enable

MAX_PB

2.5-V

D4

S3

User-defined push-button switch
(labeled as USER_2 on the board)

Table 2–5. MAX II CPLD EPM2210 System Controller Device (U10) Pin-Out (Part 4 of 5)

Schematic Signal Name

I/O

Standard

EPM2210

Pin Number

Stratix IV E

Device

Pin Number

Other

Connections

Description

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