Altera Stratix IV E FPGA Development Board - Manual (Page 62)

2–54 Chapter 2: Board Components
Memory
Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation
U3.M11 Data bus FSM_D7
2.5-V
J24 U10.R4, U2.H7
U3.D10 Data bus FSM_D8 J25 U10.N6, U2.E1
U3.D11 Data bus FSM_D9 A24 U10.T4, U2.E3
U3.E10 Data bus FSM_D10 A26 U10.M6, U2.F3
U3.E11 Data bus FSM_D11 B25 U10.R5, U2.F4
U3.F10 Data bus FSM_D12 A25 U10.P7, U2.F5
U3.F11 Data bus FSM_D13 J20 U10.T5, U2.H5
U3.G10 Data bus FSM_D14 K20 U10.N7, U2.G7
U3.G11 Data bus FSM_D15 K21 U10.R6, U2.E7
U3.D1 Data bus FSM_D16 K22 U10.M7
U3.D2 Data bus FSM_D17 C26 U10.T6
U3.E1 Data bus FSM_D18 B26 U10.P14
U3.E2 Data bus FSM_D19 J22 U10.R7
U3.F1 Data bus FSM_D20 J21 U10.P8
U3.F2 Data bus FSM_D21 C24 U10.T7
U3.G1 Data bus FSM_D22 E25 U10.N8
U3.G2 Data bus FSM_D23 D25 U10.R8
U3.J1 Data bus FSM_D24 D24 U10.F12
U3.J2 Data bus FSM_D25 A27 U10.D16
U3.K1 Data bus FSM_D26 A29 U10.F13
U3.K2 Data bus FSM_D27 C27 U10.D15
U3.L1 Data bus FSM_D28 C28 U10.F14
U3.L2 Data bus FSM_D29 E23 U10.D14
U3.M1 Data bus FSM_D30 D23 U10.E12
U3.M2 Data bus FSM_D31 B28 U10.C15
U3.A8 Address status controller SSRAM_ADSCn G20 —
U3.B9 Address status processor SSRAM_ADSPn F20 —
U3.A9 Address valid SSRAM_ADVn D21 —
U3.A7 Byte write enable SSRAM_BWEn B22 —
U3.B5 Byte lane 0 write enable SSRAM_BWn0 D22 —
U3.A5 Byte lane 1 write enable SSRAM_BWn1 E22 —
U3.A4 Byte lane 2 write enable SSRAM_BWn2 E20 —
U3.B4 Byte lane 3 write enable SSRAM_BWn3 H20 —
U3.B3 Chip enable 2 SSRAM_CE2 — —
U3.A3 Chip enable 1 SSRAM_CE1n A21 —
U3.A6 Chip enable 3 SSRAM_CE3n — —
U3.B6 Clock SSRAM_CLK C21 —
U3.N11 Data bus parity lane 0 SSRAM_DQP0 — —
Table 2–49. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Board
Reference
Description Schematic Signal
Name
I/O
Standard
Stratix IV E
Device
Pin Number
Other Connections