Altera Stratix IV E FPGA Development Board - Manual (Page 21)

Chapter 2: Board Components 2–13
Configuration, Status, and Setup Elements
May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual
The embedded USB-Blaster is automatically disabled when an external USB-Blaster is
connected to the JTAG chain.
Figure 2–4 illustrates the JTAG chain.
Each jumper shown in Figure 2–4 is located near its corresponding interface. To
connect a device or interface in the chain, the corresponding shunt must be installed
to the jumper. The FPGA, by default, is always in the chain.
1
A board must be plugged into the HSMC port in order for the chain to be contiguous.
If there is a shunt on the jumper without a board plugged in to the corresponding
HSMC port, the chain is broken and configuration cannot be performed.
The MAX II CPLD EPM2210 System Controller must be in the chain to use some of the
GUI interfaces. For this setting, place a jumper shunt on the MAX II JTAG header
(J10).
Figure 2–4. JTAG Chain
Embedded
Blaster
GPIO
TCK
EP4S530
FPGA
Analog
Switch
MAX II CPLD
EPM2210
System
Controller
HSMC
Port A
HSMC
Port B
GPIO
TMS
GPIO
TDO
GPIO
TDI
JTAG Master
GPIO
DISABLE
JTAG Master/Slave
JTAG Master/Slave
Installed
HSMC
Card
Installed
HSMC
Card
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
JTAG Slave
JTAG Slave
Analog
Switch
Analog
Switch
ENABLE
ALWAYS
ENABLED
(in chain)
Jumper
10-pin
JTAG Connector
Flash
Memory
(on install)
J10
Jumper
Jumper
Jumper
J15
J5
ENABLE
ENABLE
J4