Altera Stratix IV E FPGA Development Board - Manual (Page 46)

2–38 Chapter 2: Board Components
Components and Interfaces
Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation
Table 2–41 lists the HSMC port B interface pin assignments, signal names, and
functions.
J19.155
LVDS or CMOS clock out 2 or
CMOS bit 76
HSMA_CLK_OUT_P2
LVDS or 2.5-V
R12 —
J19.156
LVDS or CMOS clock in 2 or
CMOS bit 77
HSMA_CLK_IN_P2 U4 —
J19.157
LVDS or CMOS clock out 2 or
CMOS bit 78
HSMA_CLK_OUT_N2 T11 —
J19.158
LVDS or CMOS clock in 2 or
CMOS bit 79
HSMA_CLK_IN_N2 U3 —
J19.160 HSMC port A presence detect HSMA_PSNTn
2.5-V
— U10.F16
D4
User LED to show RX data activity
on HSMC port A
HSMA_RX_LED AK12 —
D3
User LED to show TX data activity
on HSMC port A
HSMA_TX_LED G30 —
Table 2–40. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5)
Board
Reference
Description
Schematic Signal
Name
I/O Standard
Stratix IV E
Device
Pin Number
Other
Connections
Table 2–41. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
Board
Reference
Description Schematic Signal
Name
I/O Standard
Stratix IV E
Device
Pin Number
Other
Connections
J9.1 Transceiver TX bit 7
NC 1.4-V PCML
— —
J9.2 Transceiver RX bit 7 — —
J9.3 Transceiver TX bit 7n — —
J9.4 Transceiver RX bit 7n — —
J9.5 Transceiver TX bit 6 — —
J9.6 Transceiver RX bit 6 — —
J9.7 Transceiver TX bit 6n — —
J9.8 Transceiver RX bit 6n — —
J9.9 Transceiver TX bit 5 — —
J9.10 Transceiver RX bit 5 — —
J9.11 Transceiver TX bit 5n — —
J9.12 Transceiver RX bit 5n — —
J9.13 Transceiver TX bit 4 — —
J9.14 Transceiver RX bit 4 — —
J9.15 Transceiver TX bit 4n — —
J9.16 Transceiver RX bit 4n — —
J9.17 Transceiver TX bit 3 — —
J9.18 Transceiver RX bit 3 — —
J9.19 Transceiver TX bit 3n — —
J9.20 Transceiver RX bit 3n — —