User-defined leds, User-defined leds –25 – Altera Stratix IV E FPGA Development Board User Manual

Page 33

Advertising
background image

Chapter 2: Board Components

2–25

General User Input/Output

May 2011

Altera Corporation

Stratix IV E FPGA Development Board Reference Manual

The board reference S4 is the CPU reset push-button switch, CPU_RESETn, which is an
input to the Stratix IV E FPGA device. The CPU_RESETn is intended to be the master
reset signal for the FPGA design loaded into the Stratix IV E device. The CPU_RESETn
signal must be enabled within the Quartus II software for this reset function to work.
Otherwise, the CPU_RESETn acts as a regular I/O pin. When enabled in the Quartus II
software, and then pulled high on the board, this switch resets every register within
the FPGA.

Table 2–24

lists the user-defined push-button switch schematic signal names and their

corresponding Stratix IV E FPGA device pin numbers.

Table 2–25

lists the user-defined push-button switch component reference and the

manufacturing information.

User-Defined LEDs

The development board includes general and HSMC user-defined LEDs. This section
describes all user-defined LEDs. For information on board specific or status LEDs,
refer to

“Status Elements” on page 2–15

.

Table 2–24. User-Defined Push-Button Switch Schematic Signal Names and Functions

Board

Reference

Description

Schematic Signal

Name

I/O

Standard

Stratix IV E

Device Pin

Number

Other

Connections

S1

Reset configuration push-button switch.
Driven to the MAX II CPLD System
Controller to reconfigure the FPGA from
flash memory.

RESET_CONFIGn

2.5-V

U10.R16

S2

Factory configuration push-button
switch. Driven to the MAX II CPLD
System Controller to reconfigure the
FPGA to the default factory design.

FACTORY_CONFIGn

U10.A10

S3

User-defined push-button switch. Driven
to the MAX II CPLD System Controller.

MAX_PB

(Labeled as

USER_1/USER_2

on

the board)

U10.D4

S4

CPU reset push-button switch. Driven to
the Stratix IV E device to reset the FPGA.

CPU_RESETn

Y4

S5

User-defined reset push-button switch.
Driven to MAX II CPLD and Stratix IV E
device for logic reset.

SYS_RESETn

U31

U10.M9

S6

User-defined push-button switch. Driven
to the Stratix IV E device.

USER_PB0

L17

S7

USER_PB1

F16

S8

USER_PB2

E16

S9

USER_PB3

K17

Table 2–25. User-Defined Push-button Switch Component Reference and Manufacturing Information

Board

Reference

Description

Manufacturer

Manufacturer

Part Number

Manufacturer Website

S1-S9

Push-Button
Switch

Panasonic

EVQPAC07K

www.panasonic.com/industrial/components/components.
html

Advertising