Altera Stratix IV E FPGA Development Board - Manual (Page 53)

Chapter 2: Board Components 2–45
Memory
May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual
J20.97 Data bus DDR3_DIMM_DQ43
1.5-V SSTL Class I
AK15
J20.209 Data bus DDR3_DIMM_DQ44 AP13
J20.210 Data bus DDR3_DIMM_DQ45 AM12
J20.215 Data bus DDR3_DIMM_DQ46 AN13
J20.216 Data bus DDR3_DIMM_DQ47 AP14
J20.99 Data bus DDR3_DIMM_DQ48 AH12
J20.100 Data bus DDR3_DIMM_DQ49 AJ12
J20.105 Data bus DDR3_DIMM_DQ50 AG12
J20.106 Data bus DDR3_DIMM_DQ51 AJ13
J20.218 Data bus DDR3_DIMM_DQ52 AJ10
J20.219 Data bus DDR3_DIMM_DQ53 AL8
J20.224 Data bus DDR3_DIMM_DQ54 AL7
J20.225 Data bus DDR3_DIMM_DQ55 AJ9
J20.108 Data bus DDR3_DIMM_DQ56 AN4
J20.109 Data bus DDR3_DIMM_DQ57 AP4
J20.114 Data bus DDR3_DIMM_DQ58 AP2
J20.115 Data bus DDR3_DIMM_DQ59 AP5
J20.227 Data bus DDR3_DIMM_DQ60 AM6
J20.228 Data bus DDR3_DIMM_DQ61 AN6
J20.233 Data bus DDR3_DIMM_DQ62 AL4
J20.234 Data bus DDR3_DIMM_DQ63 AM4
J20.39 Data bus DDR3_DIMM_DQ64 AP26
J20.40 Data bus DDR3_DIMM_DQ65 AP23
J20.45 Data bus DDR3_DIMM_DQ66 AP24
J20.46 Data bus DDR3_DIMM_DQ67 AN24
J20.158 Data bus DDR3_DIMM_DQ68 AE22
J20.159 Data bus DDR3_DIMM_DQ69 AE21
J20.164 Data bus DDR3_DIMM_DQ70 AD21
J20.165 Data bus DDR3_DIMM_DQ71 AE20
J20.6 Data strobe bit N0 DDR3_DIMM_DQS_N0 AM32
J20.15 Data strobe bit N1 DDR3_DIMM_DQS_N1 AP33
J20.24 Data strobe bit N2 DDR3_DIMM_DQS_N2 AP28
J20.33 Data strobe bit N3 DDR3_DIMM_DQS_N3 AM24
J20.84 Data strobe bit N4 DDR3_DIMM_DQS_N4 AP22
J20.93 Data strobe bit N5 DDR3_DIMM_DQS_N5 AJ14
J20.102 Data strobe bit N6 DDR3_DIMM_DQS_N6 AJ11
J20.111 Data strobe bit N7 DDR3_DIMM_DQS_N7 AP3
J20.42 Data strobe bit N8 DDR3_DIMM_DQS_N8 AP25
Table 2–43. DDR3 Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 5)
Board
Reference
Description
Schematic Signal Name
I/O Standard
Stratix IV E
Device
Pin Number