Altera Cyclone IV GX FPGA Development Board - Manual (Page 10)

2–2 Chapter 2: Board Components
Board Overview
Cyclone IV GX FPGA Development Board May 2013 Altera Corporation
Reference Manual
Board Overview
This section provides an overview of the Cyclone IV GX FPGA development board,
including an annotated board image and component descriptions.
Figure 2–1
provides an overview of the development board features.
Table 2–1 describes the components and lists their corresponding board references.
Figure 2–1. Overview of the Cyclone IV GX FPGA Development Board Features
Clock Input
Differential
SMAs
Connectors
(J11, J12)
System Reset
Push-Button
Switch (S5)
Select
Push-Button
Switch (S7)
DC Input
Jack (J5)
Cyclone
IV GX
FPGA
(U10)
Character
LCD
(J13)
CPU Reset
Push-Button
Switch (S6)
Power
Switch
(SW3)
Clock Input
SMA
Connector
(J10)
Ethernet LEDs
(D24-D27)
MAX II CPLD
EPM2210
System Controller
(U7)
User LEDs
(D7-D10,
D12-D15)
Flash x16
Memory (U6)
PCI Express
Edge Connector
(J14)
USB Type-B
Connector (J4)
RJ-45 Connector
(J7)
JTAG
Connector
(J6)
Configuration Done, Load,
Error, EPCS, User,
and Factory LEDs (D16-D21)
Load
Push-Button
Switch (S8)
Power LED
(D11)
HSMC Port A
(J1)
User Push-Button
Switches (S1-S4)
User DIP
Switch
(SW2)
Clock output
SMA
Connector
(J9)
HSMC Port B
(J2)
Gigabit Ethernet
(U21)
HSMC Bank Selection
Jumper (J3)
Board Settings
DIP Switch
(SW1)
DDR2A x32
(U8, U15)
EPCS
Device
(U18)
PCI Express
Control
DIP Switch
(SW4)
DDR2B x32
(U17, U19)
JTAG Chain
Select DIP
Switch (SW5)
Table 2–1. Cyclone IV GX FPGA Development Board Components (Part 1 of 3)
Board Reference Type Description
Featured Devices
U10 FPGA EP4CGX150DF31, 896-pin FBGA.
U7 CPLD EPM2210GF256, 256-pin FBGA.
Configuration, Status, and Setup Elements
J4 USB Type-B connector Connects to the computer to enable embedded USB-Blaster JTAG.
J6 JTAG connector Disables embedded blaster (for use with external USB-Blasters).
U18
EPCS128 serial configuration
device
Flash memory device with a serial interface which stores
configuration data for FPGA device that supports active serial
configuration and reloads the data to the FPGA upon power-up or
reconfiguration.