Altera Cyclone IV GX FPGA Development Board - Manual (Page 51)

Chapter 2: Board Components 2–43
Memory
May 2013 Altera Corporation Cyclone IV GX FPGA Development Board
Reference Manual
SSRAM
The SSRAM consists of a single standard synchronous SRAM device with a 100-TQFP
package footprint. This device has 4 MB of memory with a 18-bit data bus but is
implemented for non-linear burst mode using only a 16-bit data bus. The device
speed is 200 MHz single-data-rate. There is no minimum speed for this device.
This device is part of the shared FSM bus which connects to the flash memory, SRAM,
and MAX
II CPLD EPM2210 System Controller.
Table 2–40 lists the SSRAM pin assignments, signal names, and functions. The signal
names and types are relative to the Cyclone IV GX device in terms of I/O setting and
direction.
Table 2–40. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Board Reference Description
Schematic Signal Name
I/O Standard
Cyclone IV GX Device
Pin Number
U44.46 Address bus FSM_A1
1.8-V
AD6
U44.44 Address bus FSM_A2 AK29
U44.42 Address bus FSM_A3 AA21
U44.37 Address bus FSM_A4 AG25
U44.36 Address bus FSM_A5 AH5
U44.48 Address bus FSM_A6 AH27
U44.43 Address bus FSM_A7 AJ12
U44.49 Address bus FSM_A8 AF16
U44.47 Address bus FSM_A9 AH20
U44.39 Address bus FSM_A10 AK23
U44.35 Address bus FSM_A11 AH17
U44.34 Address bus FSM_A12 AB21
U44.50 Address bus FSM_A13 AF19
U44.45 Address bus FSM_A14 AF12
U44.33 Address bus FSM_A15 AG27
U44.32 Address bus FSM_A16 AK26
U44.100 Address bus FSM_A17 AH4
U44.80 Address bus FSM_A18 AK3
U44.81 Address bus FSM_A19 AH9
U44.99 Address bus FSM_A20 AG6
U44.82 Address bus FSM_A21 AK25
U44.23 Data bus FSM_D0 AK14
U44.59 Data bus FSM_D1 AE6
U44.22 Data bus FSM_D2 AG21
U44.63 Data bus FSM_D3 AE9
U44.68 Data bus FSM_D4 AK28
U44.72 Data bus FSM_D5 AD23
U44.12 Data bus FSM_D6 AG24