Altera Cyclone IV GX FPGA Development Board - Manual (Page 29)

Chapter 2: Board Components 2–21
General User Input/Output
May 2013 Altera Corporation Cyclone IV GX FPGA Development Board
Reference Manual
General User Input/Output
The development board includes several user I/O interfaces to the FPGA. This section
describes the following I/O interfaces:
■ User-defined push buttons
■ User-defined LEDs
■ User DIP switch
■ Character LCD
User-Defined Push Buttons
The development board includes four user-defined push buttons, a CPU reset push
button, and a system reset push button.
Board references S1, S2, S3, and S4 are push buttons that allow you to interact with the
Cyclone IV GX device. When you press and hold the switch, the device pin is set to
logic 0; when you release the switch, the device pin is set to logic 1. There is no board-
specific function for these general user push buttons.
The system reset push button, SYS_RESETn (S5), resets the MAX II CPLD EPM2210
System Controller.
The CPU reset push button, CPU_RESETn (S6), resets the FPGA design loaded into the
Cyclone IV GX device. This switch also acts as a regular I/O pin.
Table 2–18 lists the user-defined push button schematic signal names and their
corresponding Cyclone IV GX device pin numbers.
Table 2–19 lists the user-defined push button component reference and the
manufacturing information.
Table 2–18. User-Defined Push Button Schematic Signal Names and Functions
Board Reference Description
Schematic Signal
Name
I/O Standard
Cyclone IV GX
Device Pin Number
S4
User-defined push button. When the
switch is pressed, a logic 0 is
selected. When the switch is released,
a logic 1 is selected.
USER_PB0
1.8-V
C12
S3 USER_PB1 D11
S2 USER_PB2 F4
S1 USER_PB3 D8
S5 SYS_RESETn AF27
S6 CPU_RESETn G20
Table 2–19. User-Defined Push Button Component Reference and Manufacturing Information
Board Reference Description Manufacturer
Manufacturer
Part Number
Manufacturer Website
S1–S6 Push button Panasonic EVQPAC07K www.panasonic.com/industrial/