Altera Cyclone IV GX FPGA Development Board - Manual (Page 52)

2–44 Chapter 2: Board Components
Memory
Cyclone IV GX FPGA Development Board May 2013 Altera Corporation
Reference Manual
Table 2–41 lists the SSRAM component reference and manufacturing information.
U44.9 Data bus FSM_D7
1.8-V
AB22
U44.58 Data bus FSM_D8 AE22
U44.62 Data bus FSM_D9 AJ24
U44.19 Data bus FSM_D10 Y19
U44.18 Data bus FSM_D11 AH23
U44.69 Data bus FSM_D12 AK22
U44.13 Data bus FSM_D13 AH24
U44.8 Data bus FSM_D14 Y18
U44.73 Data bus FSM_D15 AJ13
U44.14
Flow Through or Pipeline mode;
active low
SSRAM_FTn Pulled low
U44.31
Linear Burst Order mode; active
low
SSRAM_LBOn Pulled low
U44.74
Ninth unused data bit for lower
byte lane
SSRAM_DQP0 Pulled low
U44.24
Ninth unused data bit for upper
byte lane
SSRAM_DQP1 Pulled low
U44.83
ADVn burst address counter
advance enable; active low
SSRAM_ADVn Pulled high
U44.84
Address strobe (Processor,
Cache Controller); active low
SSRAM_ADSPn Pulled high
U44.85
Address strobe (Processor,
Cache Controller); active low
SSRAM_ADSCn Pulled low
U44.86 Output enable; active low SSRAM_Gn G6
U44.87 Byte lane write enable SSRAM_BWn F8
U44.89 Clock SSRAM_CLK F11
U44.98 Chip enable 1 SSRAM_E1n C6
U44.97 Chip enable 2 SSRAM_E2 Pulled high
U44.92 Chip enable 3 SSRAM_E3n Pulled low
U44.93
Byte write enable for DQA Data
I/Os; active low
SSRAM_BAn D13
U44.94
Byte write enable for DQB Data
I/Os; active low
SSRAM_BBn D27
U44.64 Sleep enable SSRAM_ZZ Pulled low
Table 2–40. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)
Board Reference Description
Schematic Signal Name
I/O Standard
Cyclone IV GX Device
Pin Number
Table 2–41. SSRAM Component Reference and Manufacturing Information
Board
Reference
Description Manufacturer
Manufacturing
Part Number
Manufacturer Website
U44
Standard Synchronous Pipelined
SCD, 2 M × 18, 200 MHz
GSI GS832018GT-200V www.gsitechnology.com