Altera Cyclone IV GX FPGA Development Board - Manual (Page 22)

2–14 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Cyclone IV GX FPGA Development Board May 2013 Altera Corporation
Reference Manual
Flash Memory Programming
Flash memory programming is possible through a variety of methods using the
Cyclone IV GX device.
The default method is to use the factory design called the Board Update Portal. This
design is an embedded web server, which serves the Board Update Portal web page.
The web page allows you to select new FPGA designs including hardware, software,
or both in an industry-standard S-Record File (.flash) and write the design to the user
hardware page (page 1) of the flash memory over the network.
The secondary method is to use the pre-built parallel flash loader (PFL) design
included in the development kit. The development board implements the Altera PFL
megafunction for flash memory programming. The PFL megafunction is a block of
logic that is programmed into an Altera programmable logic device (FPGA or CPLD).
The PFL functions as a utility for writing to a compatible flash memory device. This
prebuilt design contains the PFL megafunction that allows you to write either page 0,
page 1, or other areas of flash memory over the USB interface using the Quartus II
software. This method is used to restore the development board to its factory default
settings.
Other methods to program the flash memory can be used as well, including the
Nios
® II processor.
f
For more information on the Nios II processor, refer to the Nios II Processor page of
the Altera website.
FPGA Configuration from Flash Memory
On either power-up or by pressing the program load push-button switch (S8), the
MAX
II CPLD EPM2210 System Controller's PFL configures the FPGA from the flash
memory hardware page 0 or 1 based on whether USER or FACTORY LED is illuminated.
The PFL megafunction reads the data from the flash memory and loads to the FPGA
using the FPP interface.
There are two pages reserved for the FPGA configuration data. The factory hardware
(page 0) is loaded upon power-up if the board settings DIP switch (SW1) is set to '0'.
Otherwise, the user hardware (page 1) is loaded. Pressing the program load
push-button switch (S8) loads the FPGA with a hardware page based on the LED
settings.
Table 2–7 defines the hardware page that loads when the program load
push-button switch (S8) is pressed.
Table 2–7. Program Load Push Button (S8) LED Settings (1)
USER LED FACTORY LED Design
OFF ON Factory hardware
ON OFF User hardware
Note to Table 2–7 :
(1) ON indicates that the LED is illuminated while OFF indicates that the LED is not illuminated.