Altera Cyclone IV GX FPGA Development Board - Manual (Page 34)

2–26 Chapter 2: Board Components
Components and Transceiver Interfaces
Cyclone IV GX FPGA Development Board May 2013 Altera Corporation
Reference Manual
Components and Transceiver Interfaces
This section describes the development board's communication ports and interface
cards relative to the Cyclone IV GX device. The development board supports the
following communication ports:
■ PCIe
■ 10/100/1000 Ethernet
■ HSMC
PCIe
The Cyclone IV GX FPGA development board fits entirely into a PC motherboard
with a ×4 PCIe slot which can accommodate a short-form PCIe add-in card. The
development board comes with a full height I/O bracket for its low profile form factor
card. This interface uses the Cyclone IV GX device's PCIe hard IP block in ×4 lane
configuration, saving logic resources for the user logic application.
f
For more information on using the PCIe hard IP block, refer to the PCI Express
Compiler User Guide .
The PCIe interface supports a channel width of ×4 as well as the connection speed of
Gen1 at 2.5 Gbps/lane.
The board’s power can be sourced entirely from the PCIe edge connector when
installed into a PC motherboard. Turn the power switch (SW3) to the ON position
when you install the board into a PC motherboard. Although the board can also be
powered by a laptop power supply for use on a lab bench, it is not recommended to
use from both supplies at the same time. Ideal diode power sharing devices have been
designed into this board to prevent damages or back-current from one supply to the
other.
The PCIE_REFCLK_P and PCIE_REFCLK_N signals are a 100-MHz differential input that
is driven from the PC motherboard onto this board through the PCIe edge connector.
This signal connects directly to a Cyclone IV GX REFCLK input pin pair. This clock is
terminated on the motherboard and therefore, no on-board termination is required.
This clock can have spread-spectrum properties that change its period between
9.847 ps to 10.203 ps. The I/O standard is High-Speed Current Steering Logic (HCSL).
1 PCIe signals and HSMC Port B XCVR signals are muxed via resistors and capacitors.
By default, the XCVR_RX_P and XCVR_RX_N channels of the FPGA are connected to the
PCIE_RX_P
and PCIE_RX_N signals, while the XCVR_TX_P and XCVR_TX_N channels are
connected to the PCIE_TX_P and PCIE_TX_N signals.