Sun Microsystems SUN STOREDGETM 5310 NAS - Manual (Page 79)

Chapter 2 NAS Head 2-33
2Ah G Off A Off Go to Big Real mode.
2Ch G G R Off Decompress INT13 module.
2Eh G G A Off Keyboard controller test: the keyboard controller input buffer is
free. Next, the BAT command will be issued to the keyboard
controller.
30h Off Off R R Swap keyboard and mouse ports, if needed.
32h Off Off A R Write command byte 8042: the initialization after the keyboard
controller BAT command test is done. The keyboard command
byte will be written next.
34h Off G R R Keyboard Init: the keyboard controller command byte is written.
Next, the pin 23 and 24 blocking and unblocking commands will
be issued.
36h Off G A R Disable and initialize the 8259 programmable interrupt controller.
38h G Off R R Detect configuration mode, such as CMOS clear.
3Ah G Off A R Chipset initialization before CMOS initialization.
3Ch G G R R Init system timer: the 8254 timer test is over. Starting the legacy
memory refresh test next.
3Eh G G A R Check refresh toggle: the memory refresh line is toggling.
Checking the 15 second on/off time next.
40h Off R Off Off Calculate CPU speed.
42h Off R G Off Init interrupt vectors: interrupt vector initialization is done.
44h Off A Off Off Enable USB controller in chipset.
46h Off A G Off Initialize SMM handler. Initialize USB emulation.
48h G R Off Off Validate NVRAM areas. Restore from backup if corrupted.
4Ah G R G Off Load defaults in CMOS RAM if bad checksum or CMOS clear
jumper is detected.
4Ch G A Off Off Validate date and time in RTC.
4Eh G A G Off Determine number of microcode patches present.
50h Off R Off R Load microcode to all CPUs.
52h Off R G R Scan SMBIOS GPNV areas.
54h Off A Off R Early extended memory tests.
56h Off A G R Disable DMA.
58h G R Off R Disable video controller.
TABLE 2-16 POST Progress LED Code Table (Port 80h Codes) (Continued)
POST
Code
Diagnostic LED Decoder
(G = green, R = red, A = amber) Description