Status byte when read by *stb – VXI 3002 User Manual
Page 67
STATUS BYTE
3-37
Status byte when read by *STB?
*SRE
*SRE?
&
&
&
&
*STB?
C0073
OR
&
e
d
d
e
d
d
e
d
d
e
d
d
e
d
d
e
d
d
e
d
d
e
d
d
3
3
3
7
7
7
5
5
5
1
1
1
2
2
2
6
6
6
4
4
4
0
0
0
&
&
<erb>
<mss>
<mav> <hsb>
<ssb>
<csb>
-
<esb>
Status Byte Register
Service Request Enable Register#
Register
Read
Command
Register
Read/Write
Commands
# Bit 6 in this register ignores data sent by *SRE and always returns 0 in response to
*SRE?
<rqs>, <esb> and <mav> are defined in IEEE 488.2
<erb> is a device defined queue summary bit indicating that the error queue is
non-empty.
<mss> is true when (Status Byte) AND (Enable register) > 0.
<esb> is the standard event register summary bit.
<mav> is 'message available' indicating that the output queue is non-empty.
<hsb> is 'hardware status' summary bit
<csb> is 'coupling status' summary bit
<ssb> is 'instrument status' summary bit
The Status Byte Register is Not cleared by the *STB? query.